upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 719

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

17.5.2 Debug trap
A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always
acknowledged.
Upon occurrence of a debug trap, the CPU performs the following processing.
(1)
Operation
<1> Saves restored PC to DBPC.
<2> Saves current PSW to DBPSW.
<3> Sets the NP, EP, and ID bits of PSW.
<4> Sets handler address (00000060H) for debug trap to PC and transfers control.
Figure 17-30 shows the debug trap processing format.
Chapter 17 Interrupt/Exception Processing Function
CPU processing
Figure 17-30: Debug Trap Processing Format
User’s Manual U16702EE3V2UD00
DBPC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
Exception processing
DBTRAP instruction
Restored PC
PSW
1
1
1
00000060H
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