MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 115

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Bus Operation
during an interrupt acknowledge cycle terminated by AVEC. The vector number supplied in
an autovector operation is derived from the interrupt level of the current interrupt. When the
AVEC signal is asserted instead of DSACKx during an interrupt acknowledge cycle, the
QUICC ignores the state of the data bus and internally generates the vector number (the
sum of the interrupt level plus 24 ($18)).
AVEC is multiplexed with IACK5. The AVEC bit in the port E pin assignment register
(PEPAR) controls whether the AVEC/IACK5 pin is used as an autovector input or as IACK5
(see Section 6 System Integration Module (SIM60) for additional information). AVEC is only
sampled during an interrupt acknowledge cycle; during all other cycles, AVEC is ignored.
Additionally, AVEC can be internally generated for external devices by programming the
autovector register (note that in this case AVEC pin will not be asserted externally). Seven
distinct autovectors can be used, corresponding to the seven levels of interrupt available
with signals IRQ7–IRQ1. Figure 4-28 shows the timing for an autovector operation.
MC68360 USER’S MANUAL
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