MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 252

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

System Integration Module (SIM60)
Assuming that the PIT wins the arbitration process, the SIM60 places the PIT 8-bit vector on
the bus. The SWT also has a user-defined interrupt vector. The PIT and SWT interrupts do
not allow autovectors. The IRQx lines can be vectored (externally supplied) or autovectored.
Arbitration for servicing interrupts is controlled by the value programmed into the interrupt
arbitration (IARB) field of the MCR. Because no two modules are allowed to share the same
IARB value and the only other module that generates interrupts (the CPM) has a fixed IARB
value (IARB = 8), the SIM60 IARB value should be programmed to a value between 1 and
7 or between 9 and 15.
The autovector register (AVR) contains bits that correspond to external interrupt levels that
require an autovector response. The SIM60 supports up to seven discrete external interrupt
requests. If the bit corresponding to an interrupt level is set in the AVR, the SIM60 returns
an internal autovector in response to the interrupt acknowledge cycle servicing that external
interrupt request. Otherwise, external circuitry must either return an interrupt vector or exter-
nally assert the external AVEC signal.
See 6.8.4 Interrupts in Slave Mode for more information.
6.3.1.2 SIMULTANEOUS SIM60 INTERRUPT SOURCES. If the possible level 7 interrupt
sources in the SIM60 are simultaneously asserted, the SIM60 will prioritize and service the
interrupts in the following order: 1) SWT, 2) PIT, and 3) external interrupts. At level 6 or less,
the PIT is higher than an external interrupt request asserted at the same level as the PIT.
6.3.1.2.1 Bus Monitor. The bus monitor ensures that each bus cycle is terminated within a
reasonable period of time. It continually checks the duration of the internal/external AS line
(TS for 68040). AS is normally negated by DSACKx, BERR, (TA or TEA for 68040).or HALT
(or AVEC during an interrupt acknowledge cycle) The bus monitor asserts BERR if the
response time is excessive on any bus cycle including interrupt acknowledge cycles. The
BME bit in the SYPCR enables the bus monitor.
The bus cycle termination response time is measured in clock cycles, and the maximum-
allowable response time is programmable. The bus monitor response time period ranges
from 128 to 1K system clocks (see Table 6-5). The value chosen by the user should be
larger than the longest possible response time of the slowest peripheral in the system.
6.3.1.2.2 Spurious Interrupt Monitor. In normal interrupt handling, one or more internal
sub-modules recognize the CPU32+ interrupt acknowledge cycle as a signal that the
CPU32+ is responding to their interrupt requests. The sub-modules then arbitrate for the
privilege of returning a vector or asserting AVEC to the CPU32+. (The SIM60 also performs
6-8
At system reset, the SIM60 has a higher priority (at the same in-
terrupt level) than the CPM. This priority can be changed if the
SIM60 value is written to be less than 8, the level of the CPM.
No two modules are allowed to have the same interrupt arbitra-
tion value.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES