MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 428

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Baud Rate Generators (BRGs)
Refer to Figure 7-36 for the BRG block diagram.
The clock input to the prescaler may be selected by the EXTC bits to come from one of three
sources: BRGCLK, CLK2, or CLK6. Each source is discussed in the following paragraphs.
The BRGCLK is generated in the QUICC clock synthesizer specifically for the four BRGs
(as well as a fifth BRG that is part of the SPI) and defaults to the system frequency (e.g., 25
MHz). However, the clock synthesizer in the SIM60 has an option to divide the BRGCLK by
1, 4, 16, or 64 before it leaves the clock synthesizer. Whatever the resulting frequency of
BRGCLK, the user may use that frequency as the input to the QUICC BRGs.
The ability to reduce the frequency of BRGCLK before it leaves the clock synthesizer is use-
ful in low-power applications. In a low-power mode, the BRG clocking could be a significant
factor in overall QUICC power consumption. Thus, if the BRGs do not need to generate high
frequencies or do not require a high resolution in the user application, a lower frequency
BRGCLK may be input to the BRGs. The user may wish to dynamically change the general
system clock frequency in the clock synthesizer (slow go mode) while still having the BRG
run at the original frequency. The BRGCLK allows this option also.
Alternatively, the user may choose the CLK2 or CLK6 pins to be the clock source. An exter-
nal pin allows flexible baud rate frequency generation, regardless of the system frequency.
Additionally, the CLK2 or CLK6 pins allow a single external frequency to become the input
7-104
• Each BRG Output May Be Routed to a Pin (e.g., BRGO1)
BRGCLK
RXD1
CLK6
CLK2
The BRG configuration register may be written at any time, re-
gardless of the BRGCLK input frequency.
Figure 7-36. Baud Rate Generator Block Diagram
EXTC
MUX
Freescale Semiconductor, Inc.
AUTOBAUD
CONTROL
For More Information On This Product,
ATB
MC68360 USER’S MANUAL
Go to: www.freescale.com
PRESCALER
DIVIDE BY
1 OR 16
DIV16
NOTE
COUNTER
CD11–CD0
1–4096
12-BIT
BRGO1
CLOCK
TO PIN
AND/OR
BANK
OF CLOCKS