MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 946

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Index
DRAM SIMM 9-8, 9-45
DRAM-SRAM Performance Summary 6-78
DREQ 7-28, 7-33, 7-40
DS 2-8, 4-4, 6-30
DSACK 2-8, 4-21, 4-41, 6-63, 6-65, 6-67, 7-
DSCLK 2-11, 5-63
DSI 2-11, 5-63
DSO 2-11, 5-65, 5-66
DSR 7-121
Dual Address Destination Write 7-46
Dual Address Mode 7-45
Dual Address Packing 7-46
Dual Address Source Read 7-45
Dual Address Transfer 7-46
Dual-Port RAM 7-8, 7-9, 9-15 , C-1
Dump Memory Block 5-70, 5-75
Dynamic Bus Sizing 4-6, 4-19
Dynamic Changes 7-140
EDX B-1, B-4
EEPROM 1-12, 7-312, 9-7, 9-45
EEST
Effects of Wait States on Instruction Timing
Enhanced Ethernet Serial Transceiver 1-9,
ENTER HUNT MODE 7-148, 7-176, 7-205,
EPROM 9-5, 9-38
Error Stack Frames 5-56, 5-57
Error-Handling 7-154, 7-209
Error-Handling Procedure 7-255
Ethernet 7-114, 7-116, 7-117, 7-178, A-1
INDEX-6
Block Diagram 7-9
CPM Sub-Module Base Addresses 3-3
Memory Map 3-2
Parameter RAM 7-10
SCC Buffer Descriptors 7-122
SCC Memory Structure 7-123
SCC parameter RAM 7-124
SMC Memory Structure 7-270
SMC Parameter RAM 7-270
SMC parameter RAM 7-270
Transparent Memory Map 7-225
Broadcast Address 7-257
43
5-86
13
7-227, 7-251, 7-280, 7-296, 7-297
1-9, 13, 7-236
E
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68356 USER’S MANUAL
Go to: www.freescale.com
Ethernet Address Recognition 7-252
Ethernet Address Recognition Flowchart 7-
Ethernet Block Diagram 7-237
Ethernet Channel Frame Reception 7-242
Ethernet Channel Frame Transmission 7-
Ethernet Command Set 7-250
CAM Interface 7-243
Collision Handling 7-254
Connecting QUICC to Ethernet 7-239
Connecting the QUICC to Ethernet 7-
EEST 7-236
Error-Handling Procedure 7-255
Ethernet Address Recognition Flowchart
Ethernet Block Diagram 7-237
Ethernet Channel Frame Reception 7-
Ethernet Channel Frame Transmission
Ethernet Controller 7-235
Ethernet Memory Map 7-246
Ethernet on QUICC 7-236
Ethernet Programming Model 7-250
Ethernet/802.3 Frame Format 7-235
First-Time User 7-238
Hash Table Algorithm 7-253
Heartbeat 7-257, 7-263
Internal and External Loopback 7-255
Interpacket Gap Time 7-254
Late Collision 7-263
Learning Ethernet on the QUICC 7-238
MC68160 7-236
Nonoctet Aligned 7-261
PB15–PB8 pins 7-243
Promiscuous 7-257
Retry Count 7-263
Sample One Byte 7-243
SCC Ethernet Example 7-266
Serial CAM Interface 7-244
Short Frame 7-261
Short Frame Padding 7-262
SIA 7-236
Tag Byte 7-245, 7-258
TCP/IP 7-235
253
241
240
7-253
242
7-241