MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 798

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Applications
When the QUICC is in slave mode, what is normally the AVEC pin (an input) becomes the
AVECO pin (an output) for use with external processors.
9.8.1.5 BUS ARBITRATION. When the QUICC is operating in slave mode with an
MC68EC030 master, the QUICC bus arbitration pins match those of the MC68EC030.
In slave mode, the QUICC does not support the read-modify-write cycle (RMC). If support
of read-modify-write is necessary, it would be necessary for the designer to implement the
functionality in external logic.
The BR output from the QUICC is sent directly to the MC68EC030 in this system. If other
bus masters were present, external hardware could determine their relative bus priority. The
BCLRO function of the QUICC is not used in this design because the BR pin is an output;
therefore, BCLRO is not needed.
The QUICC also has a bus clear in (BCLRI) signal that allows internal masters to be cleared
off the bus. This pin can be used with the MC68EC030 IPEND pin to give the MC68EC030
interrupts priority over the QUICC internal masters. This function is not implemented in the
design for the sake of using the alternate function of the pin, the RAS1DD function. How-
ever, if it were implemented, the IPEND signal from the MC68EC030 would have to be
latched and kept low by the MC68EC030 until completion of the interrupt routine. (If it was
not latched, the QUICC would take the bus back from the MC68EC030 as soon as the inter-
rupt acknowledge cycle was complete, which defeats the purpose of connecting the IPEND
pin to the BCLRI pin.)
9.8.1.6 BREAKPOINT GENERATION. In slave mode, the QUICC can be used to generate
a breakpoint signal using its breakpoint address register. This register will respond to
QUICC external master accesses.
The result of a breakpoint is the assertion of the BKPTO pin on the QUICC. In this applica-
tion, it was decided to route this output back to an interrupt input on the QUICC and generate
a nonmaskable interrupt to the MC68EC030.
9.8.1.7 BUS MONITOR FUNCTION. In slave mode, the QUICC will monitor the bus for bus
cycles that are not properly terminated. The cycles can originate from the QUICC or the
MC68EC030. If the MC68EC030 originates such a cycle and that cycle times out without an
AS, DSACKx, BERR, or HALT occurring, the QUICC will assert BERR
MC68EC030 to end the cycle.
9.8.1.8 SPURIOUS INTERRUPT MONITOR. In slave mode, the QUICC will watch for spu-
rious interrupt cycles generated by the MC68EC030, but only on the interrupt levels that the
9-78
If an MC68040 were the master, there is a special companion
mode on the QUICC which would configure the QUICC bus ar-
bitration pins to match those of the MC68040. The QUICC BR is
an output to the MC68EC030, and the QUICC BG is an input
from the MC68EC030.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
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