MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 616

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Management Controllers (SMCs)
7.11.10.2 SMC TRANSPARENT COMPARISON. As compared to the transparent modes
supported by the SCCs, the SMCs offer less functionality. This fits with their purpose of pro-
viding simpler functions and slower speeds. The SMC transparent controller does not sup-
port the following features:
The SMCs in transparent mode, however, do provide one feature not provided by the regular
SCCs. The SMCs allow a data character length option of 4 to 16 bits; whereas, the SCCs
provide a data character length of just 8 or 32 bits (determined by the RFW bit in the GSMR).
7.11.10.3 SMC TRANSPARENT MEMORY MAP. There is no protocol-specific parameter
RAM for the SMC when it is used as a transparent controller. Only the general SMC param-
eter RAM is used, which is discussed in 7.11.4 SMC Parameter RAM.
7.11.10.4 SMC TRANSPARENT TRANSMISSION PROCESSING. The transparent trans-
mitter is designed to work with almost no intervention from the CPU32+ core. When the
CPU32+ enables the SMC transmitter in transparent mode, it will start transmitting idles.
The SMC immediately polls the first BD in the transmit channel’s BD ring, and thereafter
once every character time, depending on the character length (i.e., every 4 to 16 serial
clocks). When there is a message to transmit, the SMC controller will fetch the data from
memory and start transmitting the message once synchronization is achieved.
7-292
• Continuous Transmission and Reception Modes
• Four Commands
• Independent Transmit and Receive Clocks Unless Connected to a TDM Channel of the
• CRC Generation and Checking
• Full RTS, CTS, and CD Pins—Supports One SMSYN Pin Only
• Ability To Transmit Data on Demand using the TODR
• Receiver/Transmitter in Transparent Mode While Receiver/Transmitter Executes An-
• 4-, 8-, or 16-Bit SYNC Recognition
• Internal DPLL Support
• Other Features for the SCCs As Described in the GSMR
SI
other Protocol
SMC Base + 28
SMC Base + 2A
SMC Base + 2C
SMC Base + 2E
SMC Base + 30
Freescale Semiconductor, Inc.
Table 7-14. SMC Transparent-Specific
Address
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Parameter RAM
Reserved
Reserved
Reserved
Reserved
Reserved
Name
Width
Word
Word
Word
Word
Word
Description
Reserved
Reserved
Reserved
Reserved
Reserved