MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 80

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Bus Operation
4.1.3 Address Bus (A31–A0)
The address bus signals are outputs that define the address of the byte (or the most signif-
icant byte) to be transferred during a bus cycle. The QUICC places the address on the bus
at the beginning of a bus cycle. The address is valid while AS is asserted.
4.1.4 Address Strobe (AS)
AS is an output timing signal that indicates the validity of an address on the address bus and
of many control signals. AS is asserted approximately one-half clock cycle after the begin-
ning of a bus cycle.
4.1.5 Data Bus (D31-D0)
The data bus is a bidirectional, nonmultiplexed, parallel bus that contains the data being
transferred to or from the QUICC. A read or write operation may transfer 8, 16, 24, or 32 bits
of data (one, two, three, or four bytes) in one bus cycle. During a read cycle, the data is
latched by the QUICC on the last falling edge of the clock for that bus cycle. For a write cycle,
all 32 bits of the data bus are driven, regardless of the port width or operand size. The
QUICC places the data on the data bus approximately one-half clock cycle after AS is
asserted in a write cycle.
4.1.6 Data Strobe (DS)
DS is an output timing signal that applies to the data bus. For a read cycle, the QUICC
asserts DS and AS simultaneously to signal the external device to place data on the bus.
For a write cycle, DS signals to the external device that the data to be written is valid. The
QUICC asserts DS approximately one clock cycle after the assertion of AS during a write
cycle.
4.1.7 Output Enable (OE)
OE is an output timing signal that applies to the data bus. On a read cycle, the QUICC
asserts OE to signal the external device to place data on the bus. OE is asserted during read
cycles with timing similar to AS.
OE is not shown in the diagrams in this section. Use AS timing instead during read cycles.
4.1.8 Byte Write Enable (WE0, WE1, WE2, WE3)
The upper upper write enable (WE0) indicates that the upper eight bits of the data bus (D31–
D24) contain valid data during a write cycle. The upper middle write enable (WE1) indicates
that the upper middle eight bits of the data bus (D23–D16) contain valid data during a write
cycle. The lower middle write enable (WE2) indicates that the lower middle eight bits of the
data bus (D15–D8) contain valid data during a write cycle. The lower write enable (WE3)
indicates that the lower eight bits of the data bus contain valid data during a write cycle.
4-4
MC68360 USER’S MANUAL
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