MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 49

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

SECTION 2
SIGNAL DESCRIPTIONS
This section contains brief descriptions of the QUICC input and output signals in their func-
tional groups as shown in Figure 2-1.
2.1 SYSTEM BUS SIGNAL INDEX
The QUICC system bus signals consist of two groups. The first group, listed in Table 2-1,
consists of system bus signals that exist when the QUICC is in the normal mode (CPU32+
enabled). The second group consists of system bus signals that exist when the QUICC is in
the slave mode (CPU32+ disabled). They are listed in Table 2-7 and may also be identified
in Figure 2-1 as those with an italic font. In Table 2-1, the signal name, mnemonic, and a
brief functional description are presented. For more detail on each signal, refer to the para-
graphs that discuss each signal.
2.1.1 Address Bus
The address bus consists of the following two groups. Refer to Section 4 Bus Operation for
information on the address bus and its relationship to bus operation.
2.1.1.1 ADDRESS BUS (A27–A0). This three-state bidirectional bus (along with A31–A28)
provides the address for the current bus cycle, except in the CPU address space. Refer to
Section 4 Bus Operation for more information on the CPU address space. A27 is the most
significant address signal in this group.
2.1.1.2 ADDRESS BUS (A31–A28). These pins can be programmed as the most signifi-
cant four address bits or as four byte write enables.
A31–A28—These pins can function as the most significant 4 address bits. A31 is the
most significant address signal in this group.
WE3–WE0—On a write cycle, these active-low signals indicates which byte of the 32-
bit data bus contains valid data.
WE0—Corresponds to A31 and selects data bits 31–24. Also may be referred to as UU-
WE.
WE1—Corresponds to A30 and selects data bits 23–16. Also may be referred to as UM-
WE.
WE2—Corresponds to A29 and selects data bits 15–8. Also may be referred to as LMWE.
WE3—Corresponds to A28 and selects data bits 7–0. Also may be referred to as LLWE.
Freescale Semiconductor, Inc.
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