MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 329

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Bits 7-0—Reserved - set to zero.
7.1.2 RISC Microcode Revision Number
The RISC controller writes a revision number stored in its ROM to a dual-port RAM location
called REV_num. REV_num is located in the miscellaneous parameter RAM. The other
locations are reserved for future use. The microcode rivision number only reflect the revision
of the micro code. It dose not always refrect the MASK number.
7.2 COMMAND SET
The host processor (CPU32+ or other external processor) issues commands to the RISC by
writing to the command register (CR). The CR only needs to be accessed on rare occasions.
For instance, to terminate the transmission of a frame by an SCC without waiting until the
end of the frame, a STOP TX command can be issued to an SCC through the command
register. The commands are described in general terms in the following paragraphs; they
are described in specific terms when the protocol or feature is described in detail.
The host should set the FLG bit in the CR when it issues commands. The CP clears FLG
after completing the command to indicate to the host that it is ready for the next command.
Subsequent commands to the CR may be given only after FLG is cleared. The software
reset command (issued by setting the RST bit) may be given regardless of the state of FLG,
but the host should still set FLG when setting RST.
The CR, a 16-bit, memory-mapped, read-write register, is cleared by reset.
RST—Software Reset Command
RST
ue of 0 stored in these bits gives a timer tick of 1 (1024) = 1024 general system clocks.
A value of 63 (decimal) stored in these bits gives a timer tick of 64 (1024) = 65536 gen-
eral system clocks.
15
This bit is set by the host and cleared by the CP. On execution of this command, the RST
bit and the FLG bit are cleared within two general system clocks. The RISC reset routine
is approximately 60 clocks long, but the user can begin initialization of the CP immediately
after this command is given. This command is useful when the host wants to reset the reg-
isters and parameters for all the channels (SCCs, SMCs, SPI, and PIP) as well as the
RISC processor and RISC timer tables. This command does not affect the serial interface
(SI) or the parallel I/O registers.
14
13
—
Misc Base + 00
Misc Base + 02
Misc Base + 04
Misc Base + 08
Address
12
Freescale Semiconductor, Inc.
11
For More Information On This Product,
REV_num
10
OPCODE
Name
RES
RES
RES
MC68360 USER’S MANUAL
Go to: www.freescale.com
9
8
Width
Word
Word
Long
Long
7
Microcode Revision Number
Reserved
Reserved
Reserved
6
CH NUM
Description
5
4
3
—
2
Command Set
1
FLG
0