MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 232
MC68EN360AI25VL
Manufacturer Part Number
MC68EN360AI25VL
Description
Manufacturer
Freescale
Datasheet
1.MC68EN360AI25VL.pdf
(962 pages)
Specifications of MC68EN360AI25VL
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Compliant
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Part Number:
MC68EN360AI25VL
Manufacturer:
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CPU32+
5.7.2.1 FETCH EFFECTIVE ADDRESS. The fetch EA table indicates the number of clock
periods needed for the processor to calculate and fetch the specified EA. The total number
of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock reads and writes.
5-90
MUL.L, DIV.L, CHK2, CMP2, and DBcc) are not permitted to begin until the extension
word has been in the instruction pipeline for at least one cycle. This does not apply to
long offsets or displacements.
Dn
An
(An)
(An)
(d
(xxx).W
(xxx).L
# data .B
# data .W
# data .L
(d
(0) (All Suppressed)
(d
(d
(An)
(Xm.Sz Sc)
(An,Xm.Sz Sc)
(d
(d
(d
(d
(d
(d
X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands.
For long-word bus cycles, add two clocks to the tail and to the number of cycles.
NOTES:
(An)
1. The read of the EA and replacement fetches overlap the head of the operation by the amount
2. Size and scale of the index register do not affect execution time.
3. The PC may be substituted for the base address register An.
4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the
5. Timing is calculated with the CPU32+ in 16-bit mode.
16
8
16
32
16
32
16
32
16
32
,An,Xn.Sz
,An) or (d
)
)
,An) or (d
,An) or (d
,An,Xm) or (d
,An,Xm) or (d
,An,Xm.Sz Sc) or (d
,An,Xm.Sz Sc) or (d
specified in the tail.
head until the head reaches zero, at which time additional clocks must be added to both the tail
and cycle counts.
16
16
32
Sc) or (d
,PC)
,PC)
,PC)
16
32
,PC,Xm)
,PC,Xm)
Instruction
Freescale Semiconductor, Inc.
8
,PC,Xn.Sz
16
32
For More Information On This Product,
,PC,Xm.Sz Sc)
,PC,Xm.Sz Sc)
MC68360 USER’S MANUAL
Go to: www.freescale.com
Sc)
Head
–
–
1
1
2
1
1
1
1
1
1
4
2
1
1
1
4
4
1
1
2
1
2
1
Tail
–
–
1
1
2
3
3
5
1
1
3
2
2
3
5
1
2
2
3
5
2
3
2
3
0(0/0/0)
0(0/0/0)
3(X/0/0)
3(X/0/0)
4(X/0/0)
5(X/1/0)
5(X/1/0)
7(X/2/0)
3(0/1/0)
3(0/1/0)
5(0/2/0)
8(X/1/0)
6(X/1/0)
7(X/2/0)
9(X/3/0)
5(X/1/0)
8(X/1/0)
8(X/1/0)
7(X/2/0)
9(X/3/0)
8(X/2/0)
9(X/3/0)
8(X/2/0)
9(X/3/0)
Cycles
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
Notes
1,2,4
1,2,4
1,3,4
1,3,4
1,3,4
1,3,4
1,3
1,4
1,4
1,4
–
–
1
1
1
1
1
1
1
1
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