MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 413
MC68EN360AI25VL
Manufacturer Part Number
MC68EN360AI25VL
Description
Manufacturer
Freescale
Datasheet
1.MC68EN360AI25VL.pdf
(962 pages)
Specifications of MC68EN360AI25VL
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Compliant
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The pointers provided by this register indicate the SI RAM entry word offset that is currently
in progress. The register is cleared at reset.
In all cases, the value in the TxPTR or RxPTR increments by one for each entry (i.e., 16-bit
SI RAM word) that is processed by the SI. Since each TxPTR and RxPTR is 5 bits each, the
values in each TxPTR and RxPTR can range from 0 to 31, corresponding to 32 different SI
RAM entries.
The full pointer range may not necessarily be used. For instance, if the last bit is set in the
fifth SI RAM entry, then the pointer will only reflect values from 0 to 4. Once the fifth entry is
processed by the SI, the pointer is reset to 0.
The V-bit in each entry shows that the entry is valid. This information is particularly useful if
the PTR value happens to be zero. Additionally, the V-bits save the user from having to read
both the SIRP and the SISTR to obtain the needed information.
The pointer values are described based on the four possible ways the SI RAM can be con-
figured.
7.8.5.6.1 SIRP When RDM = 00 (One Static TDM). •In this case, since 64 entries cannot
7.8.5.6.2 SIRP When RDM = 01 (One Dynamic TDM). •For the receiver, either RaPTR or
31
15
—
—
RaPTR and RbPTR contain the address of the RAM entry currently active. When the SI
services entries 1–32, RaPTR will be incremented, and RbPTR will be continuously
cleared. When the SI services entries 33–64, RaPTR will be continuously cleared, and
RbPTR will be incremented.
TaPTR and TbPTR contain the address of the Tx entry currently active. When the SI ser-
vices entries 1–32, TaPTR will be incremented, and TbPTR will be continuously cleared.
When the SI services entries 33–64, TaPTR will be continuously cleared, and TbPTR will
be incremented.
If its V-bit is set, RaPTR contains the address of the Rx entry currently active. The SI RAM
receive address block in use is 0–63, and CRORa = 0 in SISTR.
If its V-bit is set, RbPTR contains the address of the Rx entry currently active. The SI RAM
receive address block in use is 64–127, and CRORa = 1 in SISTR.
If its V-bit is set, TaPTR contains the address of the Tx entry currently active. The SI RAM
transmit address block in use is 128–191, and CROTa = 0 in SISTR.
be signified with a single 5-bit pointer, two 5-bit pointers are used—one for the first 32
entries and one for the second 32 entries.
RbPTR is used, depending on which portion of the SI Rx RAM is currently active. For
the transmitter, either TaPTR or TbPTR is used, depending on which portion of the SI
Tx RAM is currently active.
30
—
14
—
29
13
V
V
28
12
Freescale Semiconductor, Inc.
27
11
For More Information On This Product,
RbPTR
TbPTR
26
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
25
9
24
8
23
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7
22
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—
6
Serial Interface with Time Slot Assigner
21
V
V
5
20
4
19
3
RaPTR
TaPTR
18
2
17
1
16
0
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