MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 340

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

RISC Timer Tables
7.4.8 RISC Timer Interrupt Handling
The following sequence describes what would normally occur within an interrupt handler for
the RISC timer tables:
7.4.9 RISC Timer Table Algorithm
The RISC scans the timer table once every tick. For each valid timer in the timer table, the
RISC decrements the count and checks for a timeout. If no timeout occurs, it moves to the
next timer. If a timeout occurs, the RISC sets the corresponding event bit in the RISC timer
event register. It checks to see if the timer is to be restarted. If so, it leaves the timer valid
bit set in the R_TMV location and resets the current count to the initial count; otherwise, it
clears the R_TMV bit. Once the timer table is scanned, the RISC updates the TM_cnt value
in the RISC timer table parameter RAM and ceases working on the timer tables until the next
tick.
If a SET TIMER command is issued, the RISC controller makes the appropriate modifica-
tions to the timer table and parameter RAM, but does not scan the timer table until the next
tick of the internal timer. It is important to use the SET TIMER command to properly synchro-
nize the timer table alterations to the execution of the RISC.
7.4.10 RISC Timer Table Application: Track the RISC Loading
The RISC timers can be used to track the loading of the RISC controller. The following
sequence gives a method for using the 16 RISC timers to determine if the RISC controller
ever exceeds the 96% utilization level during any tick interval. Removing the timers then
adds a 4% margin to the RISC utilization level. The aggressive user can use this technique
to push the RISC performance to its limit in an application.
The user should use the standard initialization sequence, with the following differences:
7-16
1. Once an interrupt occurs, read the RISC timer event register to see which timer or tim-
2. Issue additional SET TIMER commands at this time or later, as desired. Nothing need
3. Clear the R-TT bit in the CPM interrupt status register.
4. Execute the RTE instruction.
1. Program the tick of the RISC timers to be 1024 x 16 = 16384.
2. Disable RISC timer interrupts, if desired.
3. Using the SET TIMER command, initialize all 16 RISC timers to have a timer period of
4. Program one of the four general-purpose timers to increment once every tick. The gen-
5. After hours of operation, compare the general-purpose timer to the current count of
ers have caused interrupts. The RISC timer event bits would normally be cleared at
this time.
be done if the timer is being restarted automatically for a repetitive interrupt.
$0000, which equates to 65536.
eral-purpose timer should be free-running and should have a timeout of 65536.
RISC timer 15. If RISC timer 15 is more than two ticks different from the general-pur-
pose timer, the RISC controller has, during some tick interval, exceeded the 96% uti-
Freescale Semiconductor, Inc.
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