MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 454

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Communication Controllers (SCCs)
any dynamic change in its parallel I/O ports or serial channel physical interface configura-
tion. A full reset using the RST bit in the CR is a comprehensive reset that may also be used.
7.10.10 SCC Interrupt Handling
The following describes what would normally take place within an interrupt handler for the
SCC.
7.10.11 SCC Timing Control
When the DIAG bits of the GSMR are programmed to normal operation, the CD and CTS
lines are controlled automatically by the SCC. The following paragraphs describe the behav-
ior in this mode. In the following description, the TCI bit in the GSMR is assumed to be
cleared, implying normal transmit clock operation.
7.10.11.1 SYNCHRONOUS PROTOCOLS. The RTS pin is asserted when the SCC data is
loaded into the transmit FIFO and a falling transmit clock occurs. At this point, the SCC
begins transmitting the data, once the appropriate conditions occur on the CTS pin. In all
cases, the first bit of data is the first bit of the opening flag, sync pattern, or the preamble (if
a preamble was programmed to be sent prior to the frame).
Figure 7-39 shows that the delay between RTS and data is 0 bit times, regardless of the
CTSS bit in the GSMR. This operation assumes that the CTS pin is already asserted to the
SCC or that the CTS pin is reprogrammed to be a parallel I/O line, in which case the CTS
signal to the SCC is always asserted. RTS is negated one clock after the last bit in the frame.
7-130
1. Once an interrupt occurs, the SCCE should be read by the user to see which sources
2. Process the Tx BDs to reuse them if the TX bit or TXE bit was set in SCCE. If the trans-
3. Extract data from the Rx BD if the RX, RXB, or RXF bit was set in SCCE. If the receive
4. Clear the SCCx bit in the CISR.
5. Execute the RTE instruction.
have caused interrupts. The SCCE bits that are going to be "handled" in this interrupt
handler would normally be cleared at this time.
mit speed is fast or the interrupt delay is long, more than one transmit buffer may have
been sent by the SCC. Thus, it is important to check more than just one Tx BD during
the interrupt handler. One common practice is to process all Tx BDs in the interrupt
handler until one is found with its R-bit set.
speed is fast or the interrupt delay is long, more than one receive buffer may have
been received by the SCC. Thus, it is important to check more than just one Rx BD
during the interrupt handler. One common practice is to process all Rx BDs in the in-
terrupt handler until one is found with its E-bit set.
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
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