MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 68

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
QUICC Memory Map
MBAR (SIM)
DPRBASE (DUAL-PORT RAM BASE)
DUAL-PORT RAM
4KB
REGB (REGISTER BASE) = DPRBASE + 4K
INTERNAL
4KB
REGISTERS
Figure 3-1. QUICC Memory Map
3.1 DUAL-PORT RAM MEMORY MAP
The internal 2816-byte (2560-byte on REV A and B mask) dual-port RAM is partitioned to
1792 bytes (1536 bytes on REV A and B mask) of system RAM, 256-byte microcode scratch
area, and 768 bytes of parameter RAM (see Table 3-1). Its base address, called dual-port
RAM base (DPRBASE), is the address pointed to by the MBAR.
NOTE
Rev A mask is C63T, Rev B mask are C69T, and F35G
The system RAM may be used for microcode program area, data area, and buffer descrip-
tors (BDs). It may be partitioned in several ways, allowing programmable partition sizes to
fit the system requirements. This is described in Section 7 Communication Processor Mod-
ule (CPM).
3-2
MC68360 USER’S MANUAL
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