MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 343

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

The timers may be gated/restarted by an external gate signal. There are two gate pins:
TGATE1 controls timer 1 and/or timer 2; TGATE2 controls timer 3 and/or timer 4.
Normal gate mode enables the count on a falling edge of the TGATEx pin and disables the
count on the rising edge of the TGATEx pin. Normal gate mode allows the timer to count
conditionally based on the state of the TGATEx pin.
Restart gate mode performs the same function as normal mode, except that it also resets
the counter on the falling edge of the TGATEx pin. The restart gate mode has applications
in pulse interval measurement and bus monitoring:
The gate function is enabled in the TMR, and the gate operating mode is selected in the
TGCR.
7.5.2.1 CASCADED MODE. In this mode (see Figure 7-7) two 16-bit timers can be inter-
nally cascaded to form a 32-bit counter. Timer 1 may be internally cascaded to timer 2, and
timer 3 may be internally cascaded to timer 4. Since, the decision to cascade timers is made
independently, the user may select such options as two 16-bit timers and one 32-bit timer.
The TGCR is used to put the timers into cascaded mode.
If the CAS bit is set in the TGCR, the two timers function as a one 32-bit timer with one 32-
bit TRR, one 32-bit TCR, and one 32-bit TCN. In this case, TMR1 and/or TMR3 are ignored,
and the modes are defined using TMR2 and/or TMR4. The capture will be controlled from
TIN2 or TIN4. Interrupts will be generated from TER2 or TER4.
• Pulse Measurement—The restart gate mode can measure a low pulse on the TGATEx
• Bus Monitoring—The restart gate mode can detect a signal that is abnormally stuck low.
pin. The rising edge of the TGATEx pin completes the measurement, and if TGATEx is
externally connected to TINx, causes the timer to capture the count value and generate
a rising-edge interrupt.
The bus signal should be connected to the TGATEx pin. The timer count is reset on the
falling edge of the bus signal, and if the bus signal does not go high again within the
number of user-defined clocks, an interrupt can be generated.
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 31–16
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 31–16
TGATE is internally synchronized to the system clock. If TGATE
meets the asynchronous input setup time (spec #47A) then,
when working with the internal clock, the counter will begin
counting after 1 system clock.
Figure 7-7. Timer Cascaded Mode Block Diagram
TIMER3
TIMER1
Freescale Semiconductor, Inc.
For More Information On This Product,
CAPTURE
CAPTURE
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE:
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 15–0
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 15–0
TIMER4
TIMER2
CLOCK
CLOCK
Timers