MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 637

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

The SPI receiver and transmitter are double-buffered as shown in the block diagram. This
corresponds to an effective FIFO size (latency) of 2 characters.
Note that the LSB of the SPI is labeled as data bit 0 on the serial line; whereas, other
devices, such as the MC145554 CODEC, may label the MSB as data bit 0. The QUICC SPI
bit 7 (MSB) is shifted out first.
When the SPI is not enabled in the SPMODE, it consumes minimal power.
7.12.2 SPI Key Features
The SPI contains the following key features:
• Four-Wire Interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL)
• Full-Duplex Operation
• Works with Data Characters from 4 to 16 bits in length
• Supports Back-to-Back Character Transmission and Reception
• Master or Slave SPI Modes Supported
The SPI is a superset of the MC68302 serial communications
port (SCP).
SPI MODE REG
COUNTER
IMB
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 7-80. SPI Block Diagram
PINS INTERFACE
MC68360 USER’S MANUAL
Go to: www.freescale.com
TRANSMIT_REG
NOTE
SHIFT_REGISTER
PERIPHERAL BUS
RECEIVE_REG
SPI BRG
Serial Peripheral Interface (SPI)
BRGCLK