MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 13

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

6.9.3.7
6.9.3.8
6.9.3.9
6.9.3.10
6.9.3.11
6.9.3.12
6.9.3.13
6.9.4
6.10
6.10.1
6.10.2
6.11
6.11.1
6.11.2
6.11.3
6.11.4
6.11.5
6.11.6
6.11.7
6.11.8
6.11.9
6.12
6.12.1
6.12.2
6.12.3
6.12.4
6.12.5
6.12.6
6.12.7
6.12.8
6.13
6.13.1
6.13.2
6.13.3
6.13.4
6.13.5
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
Paragraph
Number
Periodic Interrupt Timer Register (PITR)............................................... 6-38
Software Service Register (SWSR)....................................................... 6-39
CLKO Control Register (CLKOCR) ....................................................... 6-39
PLL Control Register (PLLCR) .............................................................. 6-40
Clock Divider Control Register (CDVCR) .............................................. 6-42
Breakpoint Address Register (BKAR) ................................................... 6-44
Breakpoint Control Register (BKCR)..................................................... 6-44
Port E Pin Assignment Register (PEPAR) ............................................ 6-48
Memory Controller................................................................................. 6-50
Memory Controller Key Features .......................................................... 6-50
Memory Controller Overview................................................................. 6-51
General-Purpose Chip-Select Overview (SRAM Banks)....................... 6-56
Associated Registers............................................................................. 6-56
8-, 16-, and 32-Bit Port Size Configuration............................................ 6-56
Write Protect Configuration ................................................................... 6-56
Programmable Wait State Configuration............................................... 6-56
Address and Address Space Checking................................................. 6-57
SRAM Bank Parity................................................................................. 6-57
External Master Support........................................................................ 6-57
Global (Boot) Chip-Select Operation..................................................... 6-58
SRAM Bus Error.................................................................................... 6-58
DRAM Controller Overview (DRAM Banks) .......................................... 6-58
DRAM Normal Access Support ............................................................. 6-60
DRAM Page Mode Support................................................................... 6-60
DRAM Burst Access Support ................................................................ 6-61
DRAM Bank Parity ................................................................................ 6-62
Refresh Operation ................................................................................. 6-62
DRAM Bank External Master Support................................................... 6-63
Double-Drive RAS Lines ....................................................................... 6-63
DRAM Bus Error.................................................................................... 6-63
Programming Model .............................................................................. 6-64
Global Memory Register (GMR)............................................................ 6-64
Memory Controller Status Register (MSTAT)........................................ 6-69
Base Register (BR) ............................................................................... 6-70
Option Register (OR)............................................................................. 6-74
DRAM-SRAM Performance Summary; ................................................. 6-78
Introduction.............................................................................................. 7-1
RISC Controller ....................................................................................... 7-3
Command Register Examples................................................................. 7-8
Command Execution Latency ................................................................. 7-8
RISC Controller Configuration Register (RCCR).................................... 7-4
RISC Microcode Revision Number......................................................... 7-5
Command Set ........................................................................................ 7-5
Communication Processor Module (CPM)
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Section 7
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Table of Contents
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