MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 352

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

IDMA Channels
7.6.2.2 CHANNEL MODE REGISTER (CMR). Each IDMA channel contains a 16-bit CMR
that is reset to $0000. It is used to configure most of the IDMA options.
ECO — External Control Option
SRM — Synchronous Request Mode
S/D — Single/Dual Address Transfer
7-28
ECO
15
Dual Address Mode : this bit defines which device is connected to the control signals.
Single Address Mode : this bit defines the direction of the transfer.
This bit controls how external devices may use the DREQx pin for IDMA service. This bit
is only relevant for applications that use external request mode or use the external DONEx
pin to terminate the IDMA operation.
0 = The control signals (DREQx, DACKx, and DONEx) are associated with the desti-
1 = The control signals (DREQx, DACKx, and DONEx) are associated with the source
0 = The device writes to memory, and the control signals (DREQx, DACKx, and DON-
1 = The device reads from memory, and the control signals (DREQx, DACKx, and
0 = Asynchronous request mode is selected. The DREQx and DONEx input signals
1 = Synchronous request mode is selected. The DREQx and DONEx input signals are
0 = The IDMA channel runs standard dual address transfers. Each transfer requires at
1 = The IDMA channel runs single address transfers from a peripheral to memory or
SRM
14
nation (write) portion of the transfer.
(read) portion of the transfer.
Ex) are used by the device to provide data during the destination (write) portion of
the transfer.
DONEx) are used by the device to write data during the source (read) portion of
the transfer.
are internally synchronized to the IDMA clock before they are used by the IDMA.
used by the IDMA without first being internally synchronized. This results in faster
operation, but should only be used if setup and hold times can be met.
least two bus cycles. Data packing is performed using the DHR.
from memory to a peripheral. The transfer requires one bus cycle. The DHR is not
used for these transfers because the data is transferred directly into the destination
location.
S/D
13
ue should be less than the SDMA arbitration ID so that the
SDMA channels have priority over the IDMA channels. User
must program this field to 7 when the QUICC is configured in
slave mode.
If REQG is programmed to be internal (REQG = 0X), DREQx is
ignored.
RCI
12
11
Freescale Semiconductor, Inc.
REQG
For More Information On This Product,
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
SAPI
9
DAPI
NOTE
8
7
SSIZE
6
5
DSIZE
4
3
BT
2
RST
1
STR
0