MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 423

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

CRTx bits, and program the GRx bits to transfer the D channel grant to the SCC that sup-
ports this channel. The user should mark the received bit, which is the grant bit, by program-
ming the channel select bits of the SI RAM to 111 for an internal assertion of a strobe on this
bit. This bit will be sampled by the SI and transferred to the D channel SCC as the grant.
The bit is generally bit 4 of the C/I in channel 2 of GCI, but any other bit may be selected
using the SI RAM.
For example, assuming SCC1 is connected to the D channel, SCC2 is connected to the B1
channel, and SCC4 is connected to the B2 channel, SMC1 is used to handle the C/I chan-
nels, and the D channel grant is on bit 4 of the C/I on SCIT channel 2, the initialization se-
quence is as follows:
1. Program the SI RAM. Write all entries that are not used with $0001, setting
2. SIMODE = $000080E0. Only TDMa is used; SMC1 is connected. SCIT mode is
3. SICR = $400040C0. SCC4, SCC2, and SCC1 are connected to the TSA. SCC1
4. PAODR bit 6 = 1. Configures L1TXDa to an open-drain output.
5. PAPAR bits 6, 7, and 8 = 1. Configures L1TXDa, L1RXDa, and L1RCLKa.
6. PADIR bits 6 and 7 = 1. PADIR bit 8 = 0. Configures L1TXDa, L1RXDa, and
the LST bit and disabling the routing function.
used in this example.
supports the grant mechanism since it is on the D channel.
L1RCLKa.
Since GCI requires the same routing for both receive and trans-
mit, an exact duplicate of the above entries should be written to
both the receive and transmit sections of the SI RAM beginning
at addresses 0 and 128, respectively.
If SCIT mode is not used, delete the last three entries of the SI
RAM and set the LST bit in the new last entry.
Entry
No.
1
2
3
4
5
6
7
8
SWTR
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
For More Information On This Product,
SSEL
0000
0000
0000
0000
0000
0000
0000
0000
MC68360 USER’S MANUAL
Go to: www.freescale.com
CSEL
010
100
101
001
101
000
000
111
0000
0000
0000
0001
0101
0110
0001
0000
CNT
NOTE
NOTE
RAM Word
BYT
1
1
1
0
0
1
0
0
Serial Interface with Time Slot Assigner
LST
0
0
0
0
0
0
0
1
8 Bits SMC1
6 Bits SMC1
Skip 7 Bytes
Description
8 Bits SCC2
8 Bits SCC4
2 Bits SCC1
D Grant Bit
Skip 2 Bits