MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 296

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

System Integration Module (SIM60)
for up to eight banks of DRAMs. The DRAM controller provides eight RAS lines for up to
eight DRAM banks, four CAS lines and four parity (PRTY) lines (one for each data byte on
the QUICC system bus), and a parity error signal (PERR). The DRAM controller also pro-
vides multiplexed address lines for on-chip bus masters and an address mux signal (AMUX)
to support an external address muxing for external masters that wish to use the QUICC
DRAM controller for their accesses to DRAM. The DRAM controller also fully supports an
external MC68EC040 (or other MC68040 family variations) with the signals BADD2,
BADD3, TA, TS, and TBI.
Alternatively, a general-purpose chip select may be used instead of any DRAM bank.
Some features are common to all eight memory banks. First, a full 32-bit address decode
for each memory bank is possible, with 17 bits having address masking. The full 32-bit
decode is available, even if all 32 address bits are not brought outside the QUICC. Each
memory bank includes a variable block size from 2 Kbytes up to 256 Mbytes). From 0 to 15
wait states may be programmed with DSACK generation. The memory bank can be used
by an external master, including the MC68EC040, in which case burst accesses are also
supported. Parity may be generated and checked for any memory bank (SRAM, DRAM,
etc.). Each memory bank may be selected for read-only or read/write operation. Byte-write
enable (WE) signals are available for each byte that is written to memory. Also, an output
enable (OE) signal is provided to eliminate external glue logic. Finally, the access to a mem-
ory bank may be restricted to only certain function codes for system protection. The function
code comparison occurs with a mask option also.
The memory controller functionality allows QUICC-based systems to be built very easily. For
instance, a minimal QUICC system may require no glue logic as shown in Figure 6-11. In
this example, CS0 is used for the boot EPROM, and RAS1 is used for the DRAM SIMM. The
WE signals are used to simplify the interface to the DRAM SIMM, and the OE signal is used
to simplify the interface to the EPROM. Byte parity is supported in this configuration.
6-52
When one of the eight banks of memory is configured to control
DRAM, it is referred to as a DRAM bank. When one of the eight
banks of memory is configured to control standard memory
(such as SRAM and EPROM) or a peripheral, it is referred to as
an SRAM bank. Thus, the term “SRAM bank” is used to mean
“non-DRAM” in this description.
If the WE signal of the QUICC is used to control memory write
operation, unless the memory width is 32 bit, the user must
specify the correct memory width with the SPS0-1 bits of the op-
tion register. For example, if the SPS is programed for a 16 bit
port size, only WE0 and WE1 will be asserted. If external asser-
tion of DSACK is used due to the algorithm of dynamic bus siz-
ing, the first bus cycle assumes a 32 bit port size and will output
WE for 32bit regardless of external DSACK encoding.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE:
NOTE