MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 180

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

CPU32+
5.5.1.2 EXCEPTION PROCESSING SEQUENCE. For all exceptions other than a reset
exception, exception processing occurs in the following sequence. Refer to 5.5.2.1 Reset
for details of reset processing.
As exception processing begins, the processor makes an internal copy of the SR. After the
copy is made, the processor state bits in the SR are changed—the S-bit is set, establishing
supervisor access level, and bits T1 and T0 are cleared, disabling tracing. For reset and
interrupt exceptions, the interrupt priority mask is also updated.
Next, the exception number is obtained. For interrupts, the number is fetched from CPU
space $F (the bus cycle is an interrupt acknowledge). For all other exceptions, internal logic
provides a vector number.
Next, current processor status is saved. An exception stack frame is created and placed on
the supervisor stack. All stack frames contain copies of the SR and the PC for use by RTE.
The type of exception and the context in which the exception occurs determine what other
information is stored in the stack frame.
Finally, the processor prepares to resume normal execution of instructions. The exception
vector offset is determined by multiplying the vector number by 4, and the offset is added to
the contents of the VBR to determine displacement into the exception vector table. The
exception vector is loaded into the PC. If no other exception is pending, the processor will
resume normal execution at the new address in the PC.
5.5.1.3 EXCEPTION STACK FRAME. During exception processing, the most volatile por-
tion of the current context is saved on the top of the supervisor stack. This context is orga-
nized in a format called the exception stack frame.
The exception stack frame always includes the contents of SR and PC at the time the excep-
tion occurred. To support generic handlers, the processor also places the vector offset in the
exception stack frame and marks the frame with a format code. The format field allows an
RTE instruction to identify stack information so that it can be properly restored.
The general form of the exception stack frame is illustrated in Figure 5-10. Although some
formats are peculiar to a particular M68000 family processor, format 0000 is always legal
and always indicates that only the first four words of a frame are present. See 5.5.4 CPU32+
Stack Frames for a complete discussion of exception stack frames.
5-38
SP
15
FORMAT
Freescale Semiconductor, Inc.
Figure 5-10. Exception Stack Frame
For More Information On This Product,
MC68360 USER’S MANUAL
OTHER PROCESSOR STATE INFORMATION,
Go to: www.freescale.com
PROGRAM COUNTER LOW
DEPENDING ON EXCEPTION
PROGRAM COUNTER HIGH
STATUS REGISTER
(0, 2, OR 8 WORDS)
VECTOR OFFSET
0