MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 934

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

MC68MH360 Product Brief
performance, the CPU32+ can be disabled, allowing the rest of the QUICC to operate as an
intelligent peripheral to a faster processor. The QUICC provides a special mode called
MC68040 companion mode to allow it to conveniently interface to members of the M68040
family. This two-chip solution provides a 22-MIPS performance at 25 MHz.
The CPU32+ also offers automatic byte alignment features that are not offered on the
CPU32. These features allow 16 or 32-bit data to be read or written at an odd address. The
CPU32+ automatically performs the number of bus cycles required.
D.2.2 System Integration Module (SIM60)
The SIM60 integrates general-purpose features that would be useful in almost any 32-bit
processor system. The term “SIM60” is derived from the QUICC part number, MC68360.
The SIM60 is an enhanced version of the SIM40 that exists on the MC68340 and MC68330
devices.
First, new features, such as a DRAM controller and breakpoint logic, have been added. Sec-
ond, the SIM40 was modified to support a 32-bit IMB as well as a 32-bit external system bus.
Third, new configurations, such as slave mode and internal accesses by an external master,
are supported.
Although the QUICC is always a 32-bit device internally, it may be configured to operate with
a 16-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is
supported. Bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32-
bit system bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system
bus mode.
D.2.3 Communications Processor Module (CPM)
The CPM contains features that allow the QUICC32 to excel in communications and control
applications. These features may be divided into three sub-groups:
The CP provides the communication features of the QUICC32. Included are a RISC proces-
sor, four SCCs, two SMCs, one SPI, 2.7 kbytes of dual-port RAM, an interrupt controller, a
time slot assigner, three parallel ports, a parallel interface port, four independent baud rate
generators, and fourteen serial DMA channels to support the SCCs, SMCs, and SPI.
The IDMAs provide two channels of general-purpose DMA capability. They offer high-
speed transfers, 32-bit data movement, buffer chaining, and independent request and
acknowledge logic. The RISC controller may access the IDMA registers directly in the buffer
chaining modes. The QUICC32 IDMAs are similar to, yet enhancements of, the two DMA
channels found on the MC68340 and the one IDMA channel found on the MC68302.
The four general-purpose timers on the QUICC32 are functionally similar to the two general-
purpose timers found on the MC68302. However, they offer some minor enhancements,
D-4
• Communications Processor (CP)
• Two IDMA Controllers
• Four General-Purpose Timers
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com