MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 183

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

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When the aborted bus cycle is an instruction prefetch, the processor will not initiate excep-
tion processing unless the prefetched information is used. For example, if a branch instruc-
tion flushes an aborted prefetch, that word is not accessed, and no exception occurs.
When the aborted bus cycle is a data access, the processor initiates exception processing
immediately, except in the case of released operand writes. Released write bus errors are
delayed until the next instruction boundary or until another operand access is attempted.
Exception processing for bus error exceptions follows the regular sequence, but context
preservation is more involved than for other exceptions because a bus exception can be ini-
Freescale Semiconductor, Inc.
Figure 5-11. Reset Operation Flowchart
PREFETCH 3 WORDS
(VECTOR # 0)
(VECTOR # 1)
FETCH VECTOR # 0
FETCH VECTOR # 1
OTHERWISE BEGIN
For More Information On This Product,
INSTRUCTION
OTHERWISE
OTHERWISE
EXECUTION
$7
$0
ENTRY
1
0
EXIT
S
T0,T1
I2:IO
VBR
MC68360 USER’S MANUAL
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SP
PC
BUS ERROR
BUS ERROR
BUS ERROR/
ADDRESS
ERROR
ASSERT HALT
EXIT
(DOUBLE BUS FAULT)
CPU32+