MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 81

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

The equations of the byte write enables for 32-bit port (16BM = 1) are as follows:
These signals have the same timing as AS. The equations are valid only for a 32-bit port.
The equations of the byte write enables for 16-bit port (B16M = 0) are as follows:
These signals have the same timing as AS. The equations are valid only for a 16-bit port.
WEx signals are not shown in the diagrams in this section. Use AS timing instead during
write cycles. The particular WEx signals that are active in a given bus cycle depend on which
bytes are being written.
4.1.9 Bus Cycle Termination Signals
The following signals can terminate a bus cycle.
4.1.9.1 DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACK1 AND DSACK0). Dur-
ing bus cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol.
During a read cycle, this signals the QUICC to terminate the bus cycle and to latch the data.
During a write cycle, this indicates that the external device has successfully stored the data
and that the cycle may terminate. These signals also indicate to the QUICC the size of the
port for the bus cycle just completed (see Table 4-3). Refer to 4.3.1 Read Cycle for timing
relationships of DSACK1 and DSACK0.
Additionally, the system integration module (SIM60) can be programmed to internally gen-
erate DSACK1 and DSACK0 for external accesses, eliminating logic required to generate
these signals. The SIM60 can alternatively be programmed to generate a fast termination,
providing a two-cycle external access. Refer to 4.2.6 Fast Termination Cycles for additional
information on these cycles.
4.1.9.2 BUS ERROR (BERR). This signal is also a bus cycle termination indicator and can
be used in the absence of DSACKx to indicate a bus error condition. BERR can also be
asserted in conjunction with DSACKx to indicate a bus error condition, provided it meets the
WE0 = R/W + AS + A0 + A1
WE1 = R/W + AS + not {(A1 * SIZ0) + (A0 * A1) + (A1 * SIZ1)}
WE2 = R/W + AS + not {(A0 * A1) + (A1 * SIZ0 * SIZ1) + (A1 * SIZ0 * SIZ1) +
WE3 = R/W + AS + not {(A0 * SIZ0 * SIZ1) + (SIZ0 * SIZ1) + (A0 * A1) + (A1 *
WE0 = R/W + AS + A0
WE1 = R/W + AS + (A0 * SIZ0 * SIZ1)
(A0 * A1 * SIZ0)}
SIZ1)}
Note that the WE signals are not affected by dynamic bus sizing.
External assertion of DSACKx will have no effect on which WEx
signal gets asserted.
When 16-bit mode is selected and Bit 7 of PEPAR is set, WE2
and WE3 are used as address lines A29 and A28 respectively.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Bus Operation