MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 294

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

System Integration Module (SIM60)
Bit 5—PWW
Bit 4—CAS2, CAS3/IACK3, IACK6
Bit 2—CAS0, CAS1/IACK1, IACK2
Bit 1—CS7/IACK7
Bit 0—AVEC (AVECO)/IACK5
6.10 MEMORY CONTROLLER
The memory controller is a sub-block of the SIM60 that is responsible for up to eight general-
purpose chip-select lines and the DRAM controller. The DRAM controller itself can control
up to eight memory banks.
6.10.1 Memory Controller Key Features
The key features of the memory controller are as follows:
6-50
This read-only bit is used to indicate if the WE/ADDR and the PRTY lines have been pro-
grammed by the user or are still in the three-state condition because the PEPAR register
has not been written.
• All Eight Memory Banks Support the Following:
0 = PEPAR has not been written. The WE/ADDR and the PRTY lines are still being
1 = PEPAR was written. The WE/ADDR and the PRTY lines have been programmed
0 = The CAS2 and CAS3 output functions are selected.
1 = The IACK3 and IACK6 output functions are selected.
0 = The CAS0 and CAS1 output functions are selected.
1 = The IACK1 and IACK2 output functions are selected.
0 = The CS7 output function is selected.
1 = The IACK7 output function is selected.
0 = The AVEC input function is selected in normal operation, or AVECO is selected in
1 = The IACK5 output function is selected.
—32-Bit Address Decode with 17 Bits of Address Masking
—Various Block Sizes—2 Kbytes up to 256 Mbytes
—From 0 to 15 Wait States Programmable with DSACK Generation
—Memory Bank Can Be Used by an External Master
—Supports Burst Accesses of the MC68040
—Byte Parity Generation/Checking
—Write-Protect Capability
—Four Byte-Write Enable (WE) Signals
—Output Enable (OE) Signal
—Special Options for Interfacing to Slow Peripherals
—Function Code Match with Mask Can Qualify Memory Bank Accesses
three-stated.
in the PEPAR, so the configuration choices of these pins in the PEPAR are valid.
slave mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com