MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 34

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Introduction
1.2 QUICC ARCHITECTURE OVERVIEW
The QUICC is 32-bit controller that is an extension of other members of the Motorola
M68300 family. Like other members of the M68300 family, the QUICC incorporates the inter-
module bus (IMB). (The MC68302 is an exception, having an M68000 bus on chip.) The IMB
provides a common interface for all modules of the M68300 family, which allows Motorola
to develop new devices more quickly by using the library of existing modules. Although the
IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first
device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM.
Each module utilizes the 32-bit IMB. The MC68360 QUICC block diagram is shown in Figure
1-1.
4.
1-4
Centronics is a trademark of Centronics, Inc.
• Parallel Interface Port
• 240 Pins Defined: 241-Lead Pin Grid Array (PGA) and 240-Lead Plastic Quad Flat Pack
—Centronics
—Supports Fast Connection Between QUICCs
(PQFP)
4
Interface Support
IDMAs
TWO
Freescale Semiconductor, Inc.
CPU32+
CORE
For More Information On This Product,
Figure 1-1. QUICC Block Diagram
FOURTEEN SERIAL
CHANNELS
SEVEN
SERIAL
CONTROLLER
DMAs
COMMUNICATIONS PROCESSOR
RISC
MC68360 USER’S MANUAL
Go to: www.freescale.com
TIMER SLOT
ASSIGNER
IMB (32 BIT)
CPM
CONTROLLER
DUAL-PORT
INTERRUPT
GENERATION
PROTECTION
2.5-KBYTE
FEATURES
PERIODIC
SYSTEM
OTHER
CLOCK
RAM
TIMER
FEATURES
OTHER
SIM 60
CHIP SELECTS
CONTROLLER
BREAKPOINT
INTERFACE
EXTERNAL
GENERAL-
PURPOSE
TIMERS
DRAM
LOGIC
JTAG
FOUR
AND
BUS
SYSTEM
I/F