MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 24

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Table of Contents
Paragraph
Number
7.13.9.1
7.13.9.2
7.13.9.3
7.13.9.4
7.14
7.14.1
7.14.2
7.14.3
7.14.4
7.14.4.1
7.14.4.2
7.14.4.3
7.14.4.4
7.14.5
7.14.6
7.14.7
7.14.7.1
7.14.7.2
7.14.7.3
7.14.7.4
7.14.8
7.14.9
7.14.10
7.14.10.1
7.14.10.2
7.14.10.3
7.14.10.4
7.14.10.5
7.15
7.15.1
7.15.2
7.15.2.1
7.15.2.2
7.15.2.3
7.15.3
7.15.4
7.15.5
7.15.5.1
7.15.5.2
7.15.5.3
7.15.5.4
7.15.6
7.15.6.1
7.15.6.2
xx
Port B Assignment Registers (PBPAR) ...............................................7-356
Data Direction Register (PBDIR) .........................................................7-356
Data Register (PBDAT)........................................................................7-356
Open-Drain Register (PBODR)............................................................7-356
Parallel I/O Ports..................................................................................7-356
Parallel I/O Key Features.....................................................................7-357
Parallel I/O Overview ...........................................................................7-357
Port A Pin Functions ............................................................................7-357
Port A Registers...................................................................................7-359
Port A Open-Drain Register (PAODR).................................................7-359
Port A Data Register (PADAT).............................................................7-359
Port A Data Direction Register (PADIR) ..............................................7-359
Port A Pin Assignment Register (PAPAR) ...........................................7-359
Port A Examples ..................................................................................7-360
Port B Pin Functions ............................................................................7-362
Port B Registers...................................................................................7-363
Port B Open-Drain Register (PBODR).................................................7-363
Port B Data Register (PBDAT).............................................................7-364
Port B Data Direction Register (PBDIR) ..............................................7-364
Port B Pin Assignment Register (PBPAR) ...........................................7-364
Port B Example ....................................................................................7-365
Port C Pin Functions ............................................................................7-365
Port C Registers...................................................................................7-367
Port C Data Register (PCDAT) ............................................................7-368
Port C Data Direction Register (PCDIR) ..............................................7-368
Port C Pin Assignment Register (PCPAR)...........................................7-368
Port C Special Options (PCSO) ...........................................................7-368
Port C Interrupt Control Register (PCINT) ...........................................7-369
CPM Interrupt Controller (CPIC) ..........................................................7-369
Overview ..............................................................................................7-370
CPM Interrupt Source Priorities ...........................................................7-372
SCC Relative Priority ...........................................................................7-372
Highest Priority Interrupt ......................................................................7-372
Nested Interrupts .................................................................................7-373
Masking Interrupt Sources in the CPM ................................................7-374
Interrupt Vector Generation and Calculation........................................7-375
CPIC Programming Model ...................................................................7-377
CPM Interrupt Configuration Register (CICR)......................................7-377
CPM Interupt Pending Register (CIPR) ...............................................7-379
CPM Interrupt Mask Register (CIMR) ..................................................7-380
CPM Interrupt In-Service Register (CISR) ...........................................7-380
Interrupt Handler Examples .................................................................7-381
Example 1—PC6 Interrupt Handler .....................................................7-381
Example 2—SCC1 Interrupt Handler...................................................7-381
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
Go to: www.freescale.com
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