MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 511

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

7.10.17.13 SCC STATUS REGISTER (SCCS). The SCCS is an 8-bit read-only register that
allows the user to monitor real-time status conditions on the RXD line. The real-time status
of the CTS and CD pins are part of the port C parallel I/O.
Bits 7–3—Reserved
FG—Flags
CS—Carrier Sense (DPLL)
ID—Idle Status
7.10.17.14 SCC HDLC EXAMPLE #1. The following list is an initialization sequence for an
SCC HDLC channel assuming an external clock is provided. SCC4 is used. The HDLC con-
troller is configured with the RTS4, CTS4, and CD4 pins active. The CLK7 pin is used for
both the HDLC receiver and transmitter.
While FG is cleared, the most recently received 8 bits are examined every bit time to see
if a flag is present. FG is set as soon as an HDLC flag ($7E) is received on the line. Once
FG is set, it will remain set at least 8 bit times, at which time the next 8 received bits are
examined. If another flag occurs, then FG remains set for at least another eight bits; oth-
erwise, FG is cleared and the search begins again.
The examination of the line is made after the data has been decoded by the DPLL.
This bit shows the real-time carrier sense of the line as determined by the DPLL, if it is
used.
ID is set when the RXD pin is a logic one for 15 or more consecutive bit times; it is cleared
after a single logic zero is received.
1. The SDCR (SDMA Configuration Register) should be initialized to $0740, rather than
2. Configure the port A pins to enable the TXD4 and RXD4 pins. Write PAPAR bits 6
3. Configure the port C pins to enable RTS4, CTS4, and CD4. Write PCPAR bit 3 with
4. Configure port A to enable the CLK7 pin. Write PAPAR bit 14 with a one. Write
0 = HDLC flags are not currently being received.
1 = HDLC flags are currently being received.
0 = The DPLL does not sense a carrier.
1 = The DPLL does sense a carrier.
0 = The line is not currently idle.
1 = The line is currently idle.
being left at its default value of $0000.
and 7 with ones. Write PADIR bits 6 and 7 with zeros. Write PAODR bits 6 and 7
with zeros.
one, and bits 10 and 11 with zeros. Write PCDIR bits 3, 10 and 11 with zeros.
Write PCSO bits 10 and 11 with ones.
PADIR bit 14 with a zero.
Freescale Semiconductor, Inc.
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For More Information On This Product,
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MC68360 USER’S MANUAL
Go to: www.freescale.com
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FG
Serial Communication Controllers (SCCs)
2
CS
1
ID
0