MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 55

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

RAS7/CS7—Row address select 7 or chip select 7 output signal.
IACK7—The QUICC asserts this pin to indicate a level 7 external interrupt during an inter-
rupt acknowledge cycle. Peripherals can use the IACKx strobes instead of monitoring the
address bus and function codes to determine that an interrupt acknowledge cycle is in
progress and to obtain the current interrupt level. IACKx lines need not be used when the
vector is generated internally by the QUICC. See Section 4 Bus Operation for more informa-
tion.
2.1.5.3 COLUMN ADDRESS SELECT/INTERRUPT ACKNOWLEDGE (CAS3–CAS0/
IACK6, 3, 2, 1). These pins can be programmed as four column address selects for
DRAMs or as interrupt acknowledge lines.
CAS3–CAS0—The DRAM column address select output signal enables the DRAM col-
umns:
IACK1, IACK2, IACK3, IACK6—The QUICC asserts one of these pins to indicate the level
of an external interrupt during an interrupt acknowledge cycle. Peripherals can use the
IACKx strobes instead of monitoring the address bus and function codes to determine that
an interrupt acknowledge cycle is in progress and to obtain the current interrupt level. IACKx
lines need not be used when the vector is generated internally by the QUICC. See Section
4 Bus Operation for more information.
2.1.5.4 ADDRESS MULTIPLEX (AMUX). See 2.1.7.7 Output Enable/Address Multiplex
(OE/AMUX) for more information.
2.1.6 Interrupt Request Level (
These pins are prioritized interrupt request lines. IRQ7, the highest priority, is nonmaskable;
IRQ6–IRQ1 are internally maskable interrupts. Refer to Section 5 CPU32+ for more infor-
mation on the interrupt request lines.
2.1.7 Bus Control Signals
These signals control the bus transfer operations of the QUICC. Refer to Section 4 Bus
Operation for more information on these signals.
CAS0 selects data bits 31–24.
CAS1 selects data bits 23–16.
CAS2 selects data bits 15–8.
CAS3 selects data bits 7–0.
IACK1 corresponds to CAS0.
IACK2 corresponds to CAS1.
IACK3 corresponds to CAS2.
IACK6 corresponds to CAS3.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
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IRQ7
–
IRQ1
)
Signal Descriptions