MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 459

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

If CTS is already asserted when RTS is asserted, transmission begins in two additional bit
times. If CTS is not already asserted when RTS is asserted and CTSS = 0, then transmis-
sion begins in three additional bit times. If CTS is not already asserted when RTS is asserted
and CTSS = 1, then transmission begins in two additional bit times.
7.10.12 Digital Phase-Locked Loop (DPLL)
DPLL data encoding and DPLL operations are discussed in the following paragraphs.
7.10.12.1 DATA ENCODING. Each SCC contains a DPLL unit that may be programmed to
encode and decode the SCC data as NRZ, NRZI Mark, NRZI Space, FM0, FM1, Manches-
ter, and Differential Manchester. Examples of the different encoding methods are shown in
Figure 7-43.
If it is not desired to use the DPLL, the NRZ coding may be chosen by the user in the GSMR.
The definition of the encodings are as follows:
NRZI SpaceA 1 is represented by a transition at the beginning of the bit
DIFFERENTIAL
MANCHESTER
MANCHESTER
NRZI SPACE
NRZI MARK
DATA
NRZ
FM0
FM1
duration of the bit.
of the bit.
beginning of the bit
reversed).
(i.e., the level present in the preceding bit is reversed).
NRZ
NRZI Mark
Freescale Semiconductor, Inc.
Figure 7-43. DPLL Encoding Examples
For More Information On This Product,
0
MC68360 USER’S MANUAL
Go to: www.freescale.com
A 1 is represented by a high level for the
A 0 is represented by a low level for the duration
A 1 is represented by no transition at all.
A 0 is represented by a transition at the
(i.e., the level present in the preceding bit is
1
1
Serial Communication Controllers (SCCs)
0
0
1