MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 385

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

INTB—Interrupt Breakpoint
7.7.2.2 SDMA STATUS REGISTER (SDSR). Shared by all 14 SDMA channels, the SDSR
is an 8-bit register used to report events recognized by the SDMA controller. On recognition
of an event, the SDMA sets its corresponding bit in the SDSR (regardless of the INTE, INTB,
and INTR bits in the SDCR). The SDSR is a memory-mapped register that may be read at
any time. A bit is reset by writing a one and is left unchanged by writing a zero. More than
one bit may be reset at a time, and the register is cleared by reset.
Bits 7–3—Reserved
RINT—Reserved Interrupt
SBER—SDMA Channel Bus Error
SBKP—SDMA Breakpoint
7.7.2.3 SDMA ADDRESS REGISTER (SDAR). The 32-bit read-only SDAR shows the sys-
tem address that was accessed during an SDMA bus error. It is undefined at reset.
This bit is the enable bit for the SBKP status bit in the SDSR.
This status bit is reserved for factory testing. RINT is cleared by writing a one; writing a
zero has no effect.
This bit indicates that the SDMA channel terminated with an error during a read or write
cycle. The SDMA bus error address can be read from the SDAR. SBER is cleared by writ-
ing a one; writing a zero has no effect.
This bit indicates that the breakpoint signal was asserted during an SDMA transfer. SBKP
is cleared by writing a one; writing a zero has no effect.
0 = A zero masks the interrupt generated by the corresponding bit in the SDSR. When
1 = When a breakpoint is recognized while the SDMA is bus master, the channel gen-
a breakpoint is recognized while the SDMA is bus master, the channel does not
generate an interrupt to the QUICC interrupt controller. The SBKP bit is still set in
the SDSR.
erates an interrupt to the QUICC interrupt controller and sets the SBKP bit in the
SDSR.
An interrupt will only be generated if the SDMA bit is set in the
CP interrupt mask register.
An interrupt will only be generated if the SDMA bit is set in the
CP interrupt mask register. The interrupt can suspend SDMA ac-
tivity immediately if it is programmed to be at a higher level than
the SDMA channels. Alternatively, the interrupt can be pro-
cessed after the SDMA transfer is complete.
Freescale Semiconductor, Inc.
7
For More Information On This Product,
6
MC68360 USER’S MANUAL
Go to: www.freescale.com
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5
NOTE
NOTE
4
3
RINT
2
SBER
1
SBKP
0
SDMA Channels