MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 267

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

6.7.3 Port E
Port E pins can be independently programmed to select a number of system bus signal alter-
natives, including CAS lines, WE lines, OE lines, IACK lines, etc. The port E pin assignment
register controls the function of the port E pins. See 6.9.4 Port E Pin Assignment Register
(PEPAR).
6.8 SLAVE (DISABLE CPU32+) MODE
In this mode, the CPU32+ core on the QUICC is disabled, and the QUICC functions as an
intelligent peripheral. Slave mode is enabled during system (or power-up) reset by the con-
figuration of the CONFIG pins. In slave mode, the IDMAs and SDMAs on a QUICC can still
obtain ownership of the system bus, even through the CPU32+ core is disabled. The slave
mode has several common uses:
1. A multiple QUICC system. One QUICC in the system works normally with its CPU32+
2. MC68040 companion mode. The QUICC operates solely as a peripheral to the
3. MC68040 companion mode with multiple QUICCs. In this case, multiple QUICCs can
4. QUICC is a slave to the MC68030. The QUICC operates as a peripheral to the
enabled. It is called the system master. The rest of the QUICCs are used in slave
mode as peripherals, with their CPUs disabled. The slaves would have their CONFIG
pins configured to 110.
MC68EC040 processor (or other M68040 family member). In this case, the QUICC
provides a two-chip MC68EC040 system solution. One benefit of this configuration is
that the QUICC memory controller can provide DRAM control for the MC68EC040 that
includes MC68EC040 bursting support. In an MC68EC040+QUICC system, the
QUICC’s CONFIG pins would normally be set to 011 for a 32-bit boot ROM.
be slaves to a single MC68EC040. The user then chooses one of the QUICCs to pro-
vide the DRAM control for the MC68EC040 as well as the other QUICCs. In this case,
the MC68EC040 access to the DRAM is not slowed down by the relatively slower
QUICC accesses. The first QUICC in the system would have its CONFIG pins set to
011, and the other QUICCs added to that system would have their CONFIG pins set
to 110.
MC68EC030 processor (or other MC68030 family member). The QUICC's standard
slave mode is used since its bus is an MC68030-type bus. The QUICC does not sup-
port MC68030 burst accesses. In an MC68EC030+QUICC system, the QUICC's
CONFIG pins could be set to 000, 001, or 010, depending on the boot ROM size.
The 16-bit data bus is available on the D16–D31 pins. Dynamic
bus sizing for 8- and 16-bit ports is possible with a 16-bit data
bus.
PRTY3 has a small internal pullup to pull a floating PRTY3 signal
high. Thus, the default condition of the QUICC provides a full 32-
bit data bus, with 8-, 16-, and 32-bit dynamic bus sizing possible.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
System Integration Module (SIM60)