MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 125

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

completed (during execution of the exception handler routine or later) does not cause a dou-
ble bus fault. A bus cycle that is retried does not constitute a bus error or contribute to a dou-
ble bus fault. The QUICC continues to retry the same bus cycle as long as the external
hardware requests it.
Reset can also be generated internally by the halt monitor (see Section 5 CPU32+).
4.6 BUS ARBITRATION
The bus design of the QUICC provides for a single bus master at any one time, either the
QUICC or an external device. One or more of the external devices on the bus can have the
capability of becoming bus master for the external bus and the QUICC internal bus. Bus
arbitration is the protocol by which an external device becomes bus master; the bus control-
ler in the QUICC manages the bus arbitration signals so that the QUICC has the lowest pri-
ority.
External devices that need to obtain the bus must assert the bus arbitration signals in the
sequences described in the following paragraphs. Systems that include several devices that
can become bus master require external circuitry to assign priorities to the devices, so that
when two or more external devices attempt to become bus master at the same time, the one
having the highest priority becomes bus master first. The sequence of the protocol is as fol-
lows:
BR may be issued any time during a bus cycle or between cycles. BG is asserted in
response to BR. To guarantee operand coherency, BG is only asserted at the end of an
operand transfer. (For example if any internal master such as the CPU, SDMA or IDMA on
the QUICC is writing a 32-bit operand to an 8-bit port size, BG is not asserted until the fourth
byte is written.) Additionally, BG is not asserted until the end of a read-modify-write opera-
tion (when RMC is negated) in response to a BR signal. When the requesting device
receives BG and more than one external device can be bus master, the requesting device
should begin whatever arbitration is required. When it assumes bus mastership, the external
device asserts BGACK and maintains BGACK during the entire bus cycle (or cycles) for
which it is bus master. The following conditions must be met for an external device to
assume mastership of the bus through the normal bus arbitration procedure: it must have
1. An external device asserts BR.
2. The QUICC asserts BG to indicate that the bus is available.
3. The external device asserts BGACK to indicate that it has assumed bus mastership.
The QUICC may assert the BCLRO signal for one or more of its
internal bus masters, IDMA, SDMA, or DRAM refresh cycle, or
when an interrupt request is pending on a level that is greater
than a programmable level. The user can use BCLRO to negate
the BR line asserted by an external master to reduce the inter-
rupt latency for programmable interrupt levels and to increase
the QUICC internal master arbitration priority over external mas-
ters.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Bus Operation