MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 522

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Communication Controllers (SCCs)
Due to the protocol definition, collisions should only be encountered during RTS and ENQ
frames. Once a frame's transmission is started, it is fully transmitted, regardless of whether
it collides with another frame. ENQ frames are infrequent, being sent only when a node is
powered up and enters the network. A higher level protocol controls the uniqueness and
transmission of ENQ frames.
In addition to the frame fields, LocalTalk requires that the frame be FM0 (differential
Manchester space) encoded. FM0 requires one level transition on every bit boundary. If the
value to be encoded is a logic zero, FM0 also requires a second transition in the middle of
the bit time. The purpose of the FM0 encoding is to eliminate the need to transmit clocking
information on a separate wire. With FM0, the clocking information is present whenever valid
data is present.
7.10.19.2 APPLETALK CONTROLLER KEY FEATURES. The AppleTalk controller con-
tains the following key features:
7.10.19.3 QUICC APPLETALK HARDWARE CONNECTION. The QUICC connects to
LocalTalk as shown in Figure 7-62. The QUICC interfaces to the RS-422 transceiver through
the TXD, RTS, and RXD pins. The RS-422, in turn, interfaces to the LocalTalk connector.
Although it is not shown, a passive RC circuit is recommended between the transceiver and
the connector.
The 16x overspeed clock of 3.686 MHz may be generated from an external frequency
source or from one of the baud rate generators if the resulting BRG output frequency is close
to a multiple of the 3.686-MHz frequency (within the tolerance specified by LocalTalk).
The QUICC asserts the RTS signal for the complete duration of the frame; thus, RTS may
be used to enable the RS-422 transmit driver.
7.10.19.4 APPLETALK MEMORY MAP AND PROGRAMMING MODEL. The
controller on the QUICC is implemented using the HDLC controller with certain bits set. Oth-
erwise, the user should consult 7.10.18 HDLC Bus Controller for detailed information on the
programming of HDLC.
7-198
• Superset of the HDLC Controller Features
• Provides FM0 Encoding/Decoding
• Programmable Transmission of Sync Sequence
• Automatic Postamble Transmission
• Reception of Sync Sequence Does Not Cause Extra CD Interrupts
• Reception Automatically Disabled While Transmitting a Frame
• Transmit-on-Demand Feature Expedites Frames
• Connects Directly to RS-422 Transceiver
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
AppleTalk