MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 249

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Spurious Interrupt Monitor
Software Watchdog Timer (SWT)
Periodic Interrupt Timer (PIT)
Freeze Support
Low-Power Stop Support
Low-Power Standby Support
Figure 6-2 shows a block diagram of the system configuration and protection logic.
6.3.1 System Configuration
Many aspects of the system configuration are controlled by the MCR.
For debug purposes, accesses to internal peripherals can be shown on the external bus.
This function is called show cycles. The SHEN1, SHEN0 bits in the MCR control the show
cycles. External bus arbitration can be either enabled or disabled during show cycles.
The SIM60 provides eight bus arbitration levels for determining the priority of bus access (0–
7). The SIM60 is fixed at the highest level (level 7). The CPU32+ is fixed at the lowest level
(level 0). Only the SIM60, the CPU32+, the two-channel independent direct memory access
(IDMA), and the serial direct memory access (SDMA) can be bus masters and arbitrate for
If no interrupt arbitration occurs during an interrupt acknowledge cycle, the bus error sig-
nal is asserted internally.
The SWT asserts a reset or level 7 interrupt (as selected by the system protection control
register (SYPCR)) if the software fails to service the SWT for a designated period of time
(i.e., because the software is trapped in a loop or lost). There are eight selectable timeout
periods. After a system reset, this function is enabled, selects a timeout of approximately
1 second, and asserts a system reset if the timeout is reached. The SWT may be disabled,
or its timeout period may be changed in the SYPCR; however, once SYPCR is written, it
cannot be written again until a system reset. This mechanism is used to ensure the proper
operation of the SWT.
The SIM60 provides a timer to generate periodic interrupts for use with a real-time oper-
ating system or the application software. The PIT period can vary from 122 ms to 15.94 s
(assuming a 32.768-kHz crystal is used to generate the general system clock). This func-
tion can be disabled.
The SIM60 allows control of whether the SWT and PIT should continue to run during
freeze mode.
When executing the LPSTOP instruction, the QUICC can provide reduced power con-
sumption with only the SIM60 remaining active.
In addition to the low-power stop support, the QUICC can provide low power consumption
while other modules or sub-modules are functioning. In this mode, the baud rate genera-
tors and serial ports run with a fixed frequency while the rest of the chip (including the
SIM60) runs with a divided clock.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
System Integration Module (SIM60)