MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 307

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

6.12.6 DRAM Bank External Master Support
The DRAM controller supports an external MC68EC040 as well as external MC68030-type
masters, including an external QUICC.
Whenever an external master is supported, external address multiplexing must be provided
by the user. The DRAM controller controls the multiplexing with the AMUX pin. On a normal
access, AMUX defaults high, and the upper address lines (row) should be multiplexed to the
DRAM first. After the external master outputs the full address, it asserts the AS/TS signal to
the QUICC. The DRAM controller then performs the address comparison, detects that the
access is to one of its DRAM banks, and issues the corresponding RAS signal. After the
assertion of the RAS signal, the DRAM controller continues the access and negates the
AMUX signal, controls the CAS and RAS timing, and generates the DSACK/TA signals to
terminate the access. Refer to Section 9 Applications for a description of an external master
system.
The DRAM controller supports the MC68EC040 in an optimized way. The DRAM controller
supports burst accesses made by an external MC68EC040 (or other M68040 family mem-
ber) if the BACK40 bit is set in the BR. The MC68EC040 requests a burst to be performed
with a line-fill indication on the SIZx (SIZ = 11) and TTx pins. In this case, the DRAM con-
troller performs a normal access (RAS and CAS), followed by requests to the DRAM for the
next three sequential long-word operands (CAS only). The DRAM controller automatically
increments the addresses to the DRAM using the BADDR3–BADDR2 pins.
6.12.7 Double-Drive RAS Lines
RAS1 and RAS2 have a special capability. To increase the available drive strength of these
pins, the RAS1 and RAS2 signals may be output simultaneously on two pins each. The extra
signals, called RAS1DD and RAS2DD, increase the effective drive strength of the RAS sig-
nals. This selection is made in the PEPAR.
6.12.8 DRAM Bus Error
The BERR signal may be asserted by the DRAM controller in the case of a parity error or by
the bus monitor of the SIM60 as a result of a write-protect violation. In addition, if the BERR
signal is asserted externally, it should not be asserted until at least S2 of the bus cycle if TSS
= 0 in the GMR, and until at least S4 of the bus cycle if TSS = 1 in the GMR.
user can either perform the reads in software or wait for the
DRAM refresh controller to perform these reads.
To support the MC68030 cache fill operations, the DRAM con-
troller asserts all four CAS signals during every QUICC/
MC68030-type external master read cycle to a DRAM bank.
(This includes byte or word reads by the MC68030.)
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
System Integration Module (SIM60)