MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 544

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Communication Controllers (SCCs)
7.10.21 Transparent Controller
The transparent controller allows the transmission and reception of serial data over an SCC
without any modification to that data stream. Transparent mode provides a clear channel on
which no bit-level manipulation is performed by the SCC. Any protocol run over transparent
mode is performed in software. The job of an SCC in transparent mode is to function simply
as a high-speed serial-to-parallel and parallel-to-serial converter. This mode is also referred
to as "totally transparent" or "promiscuous" operation.
There are several basic applications for transparent mode. First, some data may need to be
moved serially, but requires no protocol superimposed—for example, voice data. Second,
some board-level applications require a serial-to-parallel and parallel-to-serial conversion.
Often this is done to allow communication between chips on the same board. Third, some
applications require the switching of data without interfering with the protocol encoding itself.
For instance, in a multiplexer, data from a high-speed time-multiplexed serial stream is mul-
tiplexed into multiple low-speed data streams. The concept is to switch the data path, not
alter the protocol encoded on that data path.
By appropriately setting the GSMR, any of the SCC channels may be configured to function
in transparent mode. The QUICC can both receive and transmit the entire serial bit stream
transparently. This mode is configured by selecting the TTx and TRx bits in the in the GSMR
for the transmitter and receiver, respectively. Both bits must be set for full-duplex transpar-
ent operation.
7-220
21. Write $FFFF to the SCCE to clear any previous events.
22. Write $0013 to the SCCM to enable the TXE, TX, and RX interrupts.
23. Write $08000000 to the CIMR to allow SCC4 to generate a system interrupt. (The
24. Write $00000020 to GSMR_H4 to configure a small receive FIFO width.
25. Write $00000008 to GSMR_L4 to configure the CTS and CD pins to automatically
26. Set the PSMR4 to $0600 to configure CRC16, CRC checking on receive, and
27. Write $00000038 to GSMR_L4 to enable the SCC4 transmitter and receiver. This
Tx_BD_Length. Write $00002000 to Tx_BD_Pointer.
CICR should also be initialized.)
control transmission and reception (DIAG bits) and the BISYNC mode. Notice that
the transmitter (ENT) and receiver (ENR) have not been enabled yet.
normal operation (not transparent).
additional write ensures that the ENT and ENR bits will be enabled last.
After 5 bytes have been transmitted, the Tx BD is closed. Addi-
tionally, the receive buffer is closed after 16 bytes have been re-
ceived. Any additional receive data beyond 16 bytes will cause
a busy (out-of-buffers) condition since only one Rx BD was pre-
pared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE