MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 958

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Index
SIM (System Integration Module)
SIM40 6-1
SIM60 1-5, 4-20, 6-1, 6-12
SIMCLK 6-18
INDEX-18
TRST 2-12
TS 6-27, 6-60, 6-63, 6-68, 9-32
TXD 7-101, 7-358
VCC 2-13
VCCCLK 6-19
VCCSYN 2-13, 6-19
WE 2-9, 4-27, 6-48
WE3–WE0 2-1
XFC 2-11, 6-19
XTAL 2-10, 2-11
Breakpoint Logic 6-20
Bus Monitor 6-4, 6-8
Clock Generation 6-12
CSNT40 6-73
CSNTQ 6-73
Double Bus Fault Monitor 6-4
DRAM Controller Overview 6-58
External Bus Interface Control 6-21
Freeze Support 6-11
General-Purpose Chip-Select Overview
Interrupt Generation 6-6
Interrupt Structure 6-7
Low Power in Normal Operation 6-12
Low-Power Stop 6-11
MBAR 6-1
Memory Controller 6-50
Option Register 6-74
Periodic Interrupt Timer 6-5, 6-10
Programming Model 6-64
QUICC Internal clock signals 6-15
QUICC Memory Map 6-4
QUICC System Configuration 6-55
Reset Status 6-3
SIM40 6-1
Simultaneous SIM60 Interrupt Sources
Slave (Disable CPU32+) Mode 6-23
Software Watchdog Timer 6-5
Spurious Interrupt Monitor 6-5, 6-8
System Configuration 6-5
System Configuration and Protection 6-3
TRLXQ 6-74
6-56
6-8
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SIMODE 7-78
Simple Driver Module B-2
Simultaneous SIM60 Interrupt Sources 6-8
Single Address Mode 7-48
Single Address Transfer Example 7-48
Single Buffer 7-34
SIRP 7-88
SISTR 7-87
SIZ 2-8, 4-3, 4-8, 4-25
Slave 7-314
Slave Disable CPU32+) Mode 6-23
Slave Mode 2-14, 7-316
Slave Mode 6-26, 9-31
SMC 7-99, 7-103, 7-276, 7-291, 7-305, A-2
BR 9-50
Burst EPROM 9-38
Burst SRAM 9-41
Bus Arbitration 4-55, 9-35
Bus Clear 6-25
Bus Exceptions 4-59
Cache Modes on the MC68EC040 9-51
Disable CPU32+ 6-23
DRAM Devices 9-46
DRAM SIMM 9-45
EEPROM 9-45
EPROM 9-38
Flash EPROM 9-41
Global Chip Select 6-25
GMR 9-49
Interfacing Multiple QUICCs to an
Interrupts 6-26, 9-34
MC68EC040 to QUICC Interface 9-32
Memory Interfaces 9-37
OR 9-50
PEPAR 9-49
Pin Differences 6-26
Reset Strategy 9-34
Software Configuration 9-48
SRAM 9-41
Strategy 9-34
C/I Channel 7-307
C/I Channel Receive Buffer Descriptor
C/I Channel Transmit Buffer 7-311
Character Length 7-282, 7-298
Commands in GCI Mode 7-307
MC68EC040 9-51
7-310