MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 176

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
CPU32+
The UNLK instruction removes a stack frame from the end of the list by loading an address
into the SP and pulling the value at that address from the stack. When the instruction oper-
and is the address of the link address at the bottom of a stack frame, the effect is to remove
the stack frame from both the stack and the linked list.
5.3.6 Pipeline Synchronization with the NOP Instruction
Although the no operation (NOP) instruction performs no visible operation, it does force syn-
chronization of the instruction pipeline, since all previous instructions must complete execu-
tion before the NOP begins.
5.4 PROCESSING STATES
This section describes the processing states of the CPU32+. It includes a functional descrip-
tion of the bits in the supervisor portion of the SR and an overview of actions taken by the
processor in response to exception conditions.
5.4.1 State Transitions
The processor is always in one of four processing states: normal, background, exception, or
halted.
When the processor fetches instructions and operands or executes instructions, it is in the
normal processing state. The stopped condition, which the processor enters when a STOP
or LPSTOP instruction is executed, is a variation of the normal state in which no further bus
cycles are generated.
Background state is an alternate operational mode used for system debugging. Refer to 5.6
Development Support for more information.
Exception processing refers specifically to the transition from normal processing of a pro-
gram to normal processing of system routines, interrupt routines, and other exception han-
dlers. Exception processing includes the stack operations, the exception vector fetch, and
the filling of the instruction pipeline caused by an exception. Exception processing ends
when execution of an exception handler routine begins. Refer to 5.5 Exception Processing
for comprehensive information.
A catastrophic system failure occurs if the processor detects a bus error or generates an
address error while in the exception processing state. This type of failure halts the proces-
sor. For example, if a bus error occurs during exception processing caused by another bus
error, the CPU32+ assumes that the system is not operational and halts.
The halted condition should not be confused with the stopped condition. After the processor
executes a STOP or LPSTOP instruction, execution of instructions can resume when a
trace, interrupt, or reset exception occurs.
5.4.2 Privilege Levels
To protect system resources, the processor can operate with either of two levels of access—
user or supervisor. Supervisor level is more privileged than user level. All instructions are
5-34
MC68360 USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com