MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 131

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

4.6.5 Slave (Disable CPU32+) Mode Bus Arbitration
When configured in the slave mode, the QUICC follows the bus arbitration mechanism de-
scribed in 4.6 Bus Arbitration. When acting as one or more of the QUICC internal masters
(refresh cycles, IDMA, and SDMA), the QUICC will output the BR signal. Systems that in-
clude several devices that can become bus master require external circuitry to assign prior-
ities to the devices, so that when two or more external devices attempt to become bus
R A
STATE 5
RAB
G TV
R—BUS REQUEST
A—BUS GRANT ACKNOWLEDGE
B—BUS CYCLE IN PROGRESS
Figure 4-37. Bus Arbitration State Diagram
Freescale Semiconductor, Inc.
For More Information On This Product,
R A
R A
+
A
MC68360 USER’S MANUAL
Go to: www.freescale.com
RA
+
B
STATE 0
STATE 6
RA
STATE 2
G T
G T
G T V
G—BUS GRANT
T —THREE-STATE SIGNAL TO BUS CONTROL
V—BUS AVAILABLE TO BUS CONTROL
V
V
R
RA
RA
R A
+
AB
STATE 3
G T
V
R
Bus Operation
R A