MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 293

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Bits 14–12—SINTOUT
Bits 10–9—CF1MODE
Bit 8—IPIPE1/RAS1DD
Bit 7—A31–A28/WE0–WE3
Bit 6—OE/AMUX
These bits should only be modified from its default when the QUICC is configured in slave
(disable CPU32+) mode. They are used to program the way the interrupt controller will
assert its interrupt requests to the external logic.
These bits are used to control the CONFIG1/BCLRO/RAS2DD pin functionality.
000 = Default (Used only in CPU enable mode).
001 = Reserved.
010 = The QUICC interrupt request is the RQOUT output function on the IRQ1 pin.
011 = The QUICC interrupt request is the IOUT2–IOUT0 outputs with the standard
100 = The QUICC interrupt request is the RQOUT output function on the PRTY2 pin.
101 = The QUICC interrupt request is the IOUT2–IOUT0 outputs with the standard
110 = Reserved.
111 = Reserved.
00 = CONFIG1 input pin function is chosen.
01 = CONFIG1 input pin function is chosen.
10 = The BCLRO output function is chosen instead of the CONFIG1 pin.
11 = RAS2DD output function (RAS2 double-drive) is chosen instead of the CONFIG1
0 = If the QUICC is in normal mode, the IPIPE1 output function is selected. If the
1 = The RAS1DD output function (RAS1 double-drive) is selected.
0 = The A31–A28 input/output functions are selected.
1 = The WE0–WE3 output functions are selected.
0 = The OE output function is selected.
1 = The AMUX output function is selected.
QUICC is in slave mode, the BCLRI input function is selected.
pin.
M68000 family interrupt level encoding on the IRQ6, IRQ4, and IRQ1 pin, re-
spectively.
M68000 family interrupt level encoding on the PRTY0–PRTY2 pins, respective-
ly.
Until the low byte of PEPAR is written, the parity lines will be
three-stated. The user should write the high byte of PEPAR at
the same time that the low byte is written to avoid selecting a re-
served combination of the SINTOUT bits.
Until the low byte of PEPAR is written, the WE3–WE0/A31-28
pins are three-stated.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE
System Integration Module (SIM60)