MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 800

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Applications
9.8.2.1 QUICC MEMORY INTERFACE PINS. In this design, a number of QUICC pins are
available to the memory arrays (see Figure 9-27). These pins are active, regardless of
whether the bus cycle was originated by the MC68EC030 or by one of the QUICC DMA
cycles. The QUICC detects the MC68EC030 bus cycle by the AS pin. If the QUICC gener-
ates the bus cycle, the QUICC asserts the AS pin.
Eight CSx or RASx pins are available in the system. In this design, CS0 is used for any of
the EPROM arrays since this is the global (boot) chip select. RAS1 is used for the DRAM
arrays because of its double-drive capability. CS2/RAS2 is not used in the design and is
available for other purposes, such as a second DRAM bank. CS3 is for SRAM arrays; CS4
is for EEPROM. CS5, CS6, and CS7 are unused.
In this design, it is assumed that the full 32-bit capability of the MC68EC030 is used; thus,
all memory arrays are 32 bits wide. (The only exception to this is the EEPROM, which is han-
dled differently. See 9.8.2.4 EEPROM.)
This application note does not use the parity support provided by the QUICC. Therefore, the
PRTY3–PRTY0 lines are available for their alternate functions. Parity support is available
only if the SYNC bit in the GMR is set.
The QUICC does not internally support MC68EC030 external master bursting. If the user
wishes to implement bursting on a particular memory array, the bursting support must be
generated externally.
The DRAM arrays require the four CAS3–CAS0 pins. Also, since an external address mul-
tiplexer is used, the AMUX pin is required to select between rows and columns. If, however,
the user's configuration does not require DRAM, the AMUX pin can be used as an OE pin
instead. This would save an inverter in a number of memory arrays, making the memory
interface completely glueless.
The QUICC also provides four write enable (WEx) pins to select the correct byte during write
operations.
9.8.2.2 REGULAR EPROM OR FLASH EPROM. Figure 9-28 shows the glueless interface
to standard boot EPROM in the system. The assumption is made that only the MC68EC030
will access this array. The MC68EC030 offers dynamic bus sizing on-chip; thus, only an 8-
bit EPROM is required. The CONFIG2–CONFIG0 pins on the QUICC can be pulled low
through resistors to select slave mode with an 8-bit port size for the global chip select. The
QUICC will support DSACKx generation to the MC68030 according to an 8-bit port size.
9-80
Many memory arrays show an inverter on the R/W pin to create
the OE signal. When using multiple memory arrays, it is possible
to share one inverter between multiple memory arrays; however,
this configuration is not shown.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE