MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 532

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Communication Controllers (SCCs)
receiver is not in hunt mode and a SYNC character has been received, the receiver will dis-
card this character if the valid bit is set.
7.10.20.8 BDLE-BISYNC DLE REGISTER. The 16-bit, memory-mapped, read-write BDLE
register is used to define the BISYNC stripping and insertion of the DLE character. When
the BISYNC controller is in transparent mode and an underrun occurs during message
transmission, the BISYNC controller inserts DLE-SYNC pairs until the next data buffer is
available for transmission.
When the BISYNC receiver is in transparent mode and a DLE character is received, the
receiver discards this character and excludes it from the BCS if the valid bit is set. If the sec-
ond (next) character is a SYNC character, the BISYNC controller discards it and excludes it
from the BCS. If the second character is a DLE, the BISYNC controller will write it to the
buffer and include it in the BCS. If the character is not a DLE or SYNC, the BISYNC control-
ler will examine the control characters table and act accordingly. If the character is not in the
table, the buffer will be closed with the DLE follow character error (DLE) bit set. If the valid
bit is not set, the receiver will treat the character as a normal character.
7.10.20.9 TRANSMITTING AND RECEIVING THE SYNCHRONIZATION SEQUENCE.
The BISYNC channel can be programmed to transmit and receive a synchronization pat-
tern. The pattern is defined in the DSR. The length of the SYNC pattern is defined in the
SYNL bits in the GSMR. The receiver synchronizes on the synchronization pattern that is
located in the DSR. If the SYNL bits specify a non-zero synchronization pattern, then the
transmitter sends the entire contents of the DSR prior to each frame, starting with the LSB
first. Thus, the user may wish to repeat the desired SYNC pattern in the other DSR bits as
well.
7-208
15
15
15
15
15
V
V
14
14
14
14
14
4-BIT SYNC
0
0
13
13
13
13
13
When using 7-bit characters with parity, the parity bit should be
included in the SYNC register value.
When using 7-bit characters with parity, the parity bit should be
included in the DLE register value.
0
0
12
12
12
12
12
8-BIT SYNC
0
0
11
11
11
11
11
Freescale Semiconductor, Inc.
0
0
For More Information On This Product,
10
10
10
10
10
0
0
MC68360 USER’S MANUAL
Go to: www.freescale.com
9
0
9
0
9
9
9
16-BIT SYNC
NOTE
NOTE
8
0
8
0
8
8
8
7
7
7
7
7
6
6
6
6
6
5
5
5
5
5
4
4
4
4
4
SYNC
DLE
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0