MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 321

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

TCYC3–TCYC0—Cycle Length in Clocks
This field determines the length of a bus cycle (see Table 6-14). Both internal masters and
external masters use this field for their accesses to a given memory bank. In addition, an
external MC68040 uses this field for the first access of a burst access sequence.
Although TCYC3–TCYC0 is the main parameter for determining cycle length since it se-
lects the number of wait states inserted in the cycle, the total cycle length may vary for
other reasons, such as a DRAM page hit, DRAM page miss, or whether the bus master
is internal or external to the QUICC. Besides TCYC, other bits that can affect the total cy-
cle length in certain situations are WBT40, WBTQ, DWQ, DW40, EMWS, SYNC, and
TSS40 in the GMR, and TRLXQ, PGME, and BCYC in the OR. CSNTQ and CSNT40 af-
fect the CS timing, but do not affect the total cycle length.
If the user has selected an external DSACKx or TA response for this memory bank, with
the SPS or DPS bits, then TCYC3–TCYC0 are not used.
TCYC =
15
…
0
1
2
3
4
5
6
If two chip selects are programmed to assert in the same ad-
dress region, only the lower chip select (or RAS line) will assert.
External cycles are always three clocks or longer. SeeTable 6-
11 for more details.
Normal DRAM cycles are three clocks when TCYC=0 and four
clocks when TCYC=1, etc. Therefore fast termination is not pos-
sible during the initial access to DRAM. Two clock DRAM cycles
are only possible when page mode is enabled for an internal
master.
If an external DSACK response is selected with either DPS in
the GMR or SPS in the OR, TCYC should not be set to zero.
For example, CS1 has priority over CS4.
Number
Number of Clocks
…
17
2
3
4
5
6
7
8
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 6-14. Cycle Length in Clocks
Fast Termina-
Internal QUICC Master Memory Bus Cycle Length
Comments
Normal
MC68360 USER’S MANUAL
Go to: www.freescale.com
tion
NOTES
Number of Wait States
Number
…
14
0
1
2
3
4
5
*
(SRAM)
Comments
Undefined
System Integration Module (SIM60)
Number of Wait States
Numbers
(DRAM)
…
18
3
4
5
6
7
8
9