MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 310

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

System Integration Module (SIM60)
WBT40—Wait Between Transfers (MC68EC040)
WBTQ—Wait Between Transfers (QUICC-Type)
DWQ—Delay Write for QUICC (DRAM Bank Only)
The following bits are used for SRAM bank properties:
DW40—Delay Write for 040 (SRAM Bank Only)
6-66
This attribute guarantees a minimum negation time for RAS when the QUICC DRAM con-
troller is used by an external MC68EC040 master. It is used to comply with the RAS pre-
charge time in DRAMs.
The user would normally decide whether to set the TSS40 bit before setting this bit.
This attribute guarantees a minimum negation time for RAS when the QUICC DRAM con-
troller is used by one of the internal masters or by an external master of the MC68030-
type (includes an external QUICC). It is used to comply with the RAS precharge time in
DRAMs.
This attribute is used to add a clock to the assertion and negation of the CAS signal on
DRAM page hit write cycles. The write cycle lasts one additional clock in this case. This
attribute is applicable to an internal QUICC master and to an external MC68030/QUICC.
This attribute should be set if an additional wait state is necessary for SRAM write cycles.
This attribute is applicable only to an external MC68040 writing to a non-DRAM bank.
0 = RAS is negated for 4 phases of the QUICC system clock (3 phases if
1 = RAS is negated for 6 phases (5 phases if TSS40 = 1).
0 = RAS is negated for 4 phases (3 phases in page mode—PGME = 1).
1 = RAS is negated for 6 phases (5 phases in page mode—PGME = 1).
0 = Reads and writes are the same length.
1 = Add one clock to write cycles for DRAM banks where TCYC is set to 01.
0 = Reads and writes are the same length.
1 = Insert one additional wait state to MC68040 write cycles to SRAM banks.
TSS40 = 1).
The DRAM controller does not support an external TA response
for the MC68040 burst mode. Also, for non-burst MC68040 cy-
cles, TA cannot be externally asserted before RAS is asserted.
TSS40 affects the WBT40 value in order to gain back one of the
two phases that was lost by setting TSS40 = 1. This “gain back”
only applies to back-to-back DRAM cycles.
This bit must be set by the user if page mode is enabled for this
DRAM bank (PGME = 1), or else the DRAM may latch invalid
data during writes.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE