MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 60

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Signal Descriptions
signal is the serial clock used to transfer commands/status to and from the CPU32+ during
background debug mode.
2.1.11.5 FREEZE/INITIAL CONFIGURATION (FREEZE/CONFIG2). This pin can be pro-
grammed as the freeze output or as the initial configuration pin 2 input signal during system
reset.
FREEZE—Assertion of this active-high output signal indicates that the CPU32+ has
acknowledged a breakpoint and has initiated background mode operation.
CONFIG2—See 2.1.13 Initial Configuration Pins (CONFIG) for the description.
2.1.12 Test Signals
The following signals are used with the on-board test logic . See Section 8 Scan Chain Test
Access Port for more information on the use of these signals.
2.1.12.1 TRI-STATE SIGNAL (TRIS). TThe TRIS pin is enabled as a tristate control pin
only when the CPU32+ is enabled, and it is not sampled during reset. When asserted, TRIS
immediately tristates the pins.
2.1.12.2 TEST RESET (TRST). This input provides asynchronous reset to the test logic.
2.1.12.3 TEST CLOCK (TCK). This input provides a clock for on-board test logic.
2.1.12.4 TEST MODE SELECT (TMS). This input controls test mode operations for on-
board test logic.
2.1.12.5 TEST DATA IN (TDI). This input is used for serial test instructions and test data
for on-board test logic.
2.1.12.6 TEST DATA OUT (TDO). This output is used for serial test instructions and test
data for on-board test logic.
2.1.13 Initial Configuration Pins (CONFIG)
The CONFIG2–CONFIG0 pins select the QUICC initial configuration during reset (see Table
2-6). They decide whether the CPU32+ core will be enabled or disabled, the global chip
select port will be 8-, 16-, or 32-bits, and the MBAR address will be $003FF00 or
$0033FF04. After reset, these pins may be programmed to their other function. The
CONFIG2–CONFIG0 lines have internal pullup resistors so that if they are left floating, the
default selection will be 111. See Section 6 System Integration Module (SIM60) for more
information.
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