MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 105
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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4.3
The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches from
the ColdFire core and certain memory fetches initiated by the debug module. Typically, the debug module's
memory references appear as supervisor data accesses but the unit can be programmed to generate
user-mode accesses and/or instruction fetches. The cache processes any fetch access in the normal manner.
4.3.1
Because the cache and high-speed SRAM module are connected to the ColdFire core's local data bus,
certain user-defined configurations can result in simultaneous fetch processing.
Freescale Semiconductor
31–24
23–16
14–13
Field
12–7
BWE
4–3
1–0
CM
WP
AM
SM
AB
EN
15
6
5
2
Functional Description
Address base. This 8-bit field is compared to address bits [31:24] from the processor's local bus under control of the
ACR address mask. If the address matches, the attributes for the memory reference are sourced from the given ACR.
Address mask. Masks any AB bit. If a bit in the AM field is set, the corresponding bit of the address field comparison
is ignored.
ACR Enable. Hardware reset clears this bit, disabling the ACR.
0 ACR disabled
1 ACR enabled
Supervisor mode. Allows the given ACR to be applied to references based on operating privilege mode of the
ColdFire processor. The field uses the ACR for user references only, supervisor references only, or all accesses.
00 Match if user mode
01 Match if supervisor mode
1x Match always—ignore user/supervisor mode
Reserved, must be cleared.
Cache mode.
0 Caching enabled
1 Caching disabled
Buffered write enable. Defines the value for enabling buffered writes. If BWE is cleared, the termination of an operand
write cycle on the processor's local bus is delayed until the system bus cycle is completed. Setting BWE terminates
the write cycle on the local bus immediately and the operation is then buffered in the bus controller. In this mode,
operand write cycles are effectively decoupled between the processor's local bus and the system bus.
Generally, the enabling of buffered writes provides higher system performance but recovery from access errors may
be more difficult.
For the V2 ColdFire core, the reporting of access errors on operand writes is always imprecise, and enabling buffered
writes simply decouples the write instruction from the signaling of the fault even more.
0 Writes are not buffered.
1 Writes are buffered.
Reserved, must be cleared.
Write protect. Defines the write-protection attribute. If the effective memory attributes for a given access select the
WP bit, an access error terminates any attempted write with this bit set.
0 Read and write accesses permitted
1 Only read accesses permitted
Reserved, must be cleared.
Interaction with Other Modules
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 4-5. ACRn Field Descriptions
Description
Cache
4-7
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