MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 277

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Table 15-4
Freescale Semiconductor
Reset
Field
15-14
Addr
10–9
R/W
Bits
8–0
13
12
11
Name
15
RTIM Refresh timing. Determines the timing operation of auto-refresh in the SDRAM controller. Specifically,
describes DCR fields.
NAM No address multiplexing. Some implementations require external multiplexing. For example, when
COC Command on SDRAM clock enable (SCKE). Implementations that use external multiplexing (NAM = 1)
RC
—
IS
—
14
Reserved, should be cleared.
linear addressing is required, the SDRAM should not multiplex addresses on SDRAM accesses.
0 The SDRAM controller multiplexes the external address bus to provide column addresses.
1 The SDRAM controller does not multiplex the external address bus to provide column addresses.
must support command information to be multiplexed onto the SDRAM address bus.
0 SCKE functions as a clock enable; self-refresh is initiated by the SDRAM controller through
1 SCKE drives command information. Because SCKE is not a clock enable, self-refresh cannot be
Initiate self-refresh command.
0 Take no action or issue a
1 If DCR[COC] = 0, the SDRAM controller sends a
it determines the number of bus clocks inserted between a
command. This same timing is used for both memory blocks controlled by the SDRAM controller. This
corresponds to t
00 3 clocks
01 6 clocks
1x 9 clocks
Refresh count. Controls refresh frequency. The number of bus clocks between refresh cycles is
(RC + 1) x 16. Refresh can range from 16–8192 bus clocks to accommodate both standard and
low-power SDRAMs with bus clock operation from less than 2 MHz to greater than 50 MHz.
The following example calculates RC for an auto-refresh period for 4096 rows to receive 64 ms of
refresh every 15.625 µs for each row (1031 bus clocks at 66 MHz). This operation is the same as in
asynchronous mode.
# of bus clocks = 1031 = (RC field + 1) x 16
RC = (1031 bus clocks/16) -1 = 63.44, which rounds to 63; therefore, RC = 0x3F.
DCR[IS].
used (setting DCR[IS]). Thus, external logic must be used if this functionality is desired. External
multiplexing is also responsible for putting the command information on the proper address bit.
in low-power, self-refresh state where they remain until IS is cleared. When IS is cleared, the
controller sends a
suspended while the SDRAMs are in self-refresh; the SDRAM controls the refresh period.
NAM COC
13
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
12
RC
Figure 15-2. DRAM Control Register (DCR)
in the SDRAM specifications.
11
IS
SELFX
Table 15-4. DCR Field Descriptions
command for the SDRAMs to exit self-refresh. The refresh counter is
10
SELFX
RTIM
command to exit self refresh.
9
IPSBAR + 0x040
Uninitialized
8
R/W
Description
SELF
command to both SDRAM blocks to put them
REF
command and the next possible
Synchronous DRAM Controller Module
RC
ACTV
0
15-5