MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 331
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 331 of 766
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17.4.17 Descriptor Group Upper Address Register (GAUR)
GAUR contains the upper 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a multicast address. You must initialize this register.
17.4.18 Descriptor Group Lower Address Register (GALR)
GALR contains the lower 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a multicast address. You must initialize this register.
Freescale Semiconductor
GADDR1
IADDR2
Field
Field
31–0
31–0
IPSBAR
IPSBAR
IPSBAR
Offset:
Offset:
Offset:
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast
address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains
hash index bit 32.
W
W
W
R
R
R
0x111C
0x1120
0x1124
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Figure 17-16. Descriptor Individual Lower Address Register (IALR)
Figure 17-17. Descriptor Group Upper Address Register (GAUR)
Figure 17-18. Descriptor Group Lower Address Register (GALR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 17-21. GAUR Field Descriptions
Table 17-20. IALR Field Descriptions
Description
Description
GADDR1
GADDR2
IADDR2
8
8
8
7
7
7
Access: User read/write
Access: User read/write
Access: User read/write
Fast Ethernet Controller (FEC)
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
17-21
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